Configurable IC for Parallel SSD Testing
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Solution Overview
Problem
Current PC-based testers for solid state storage devices face performance and parallelism limitations, leading to costly upgrades and inefficiencies in testing due to shared-resource architectures and bottlenecks in data transmission.
Innovation Solution
A system utilizing a configurable integrated circuit (IC), such as an FPGA, provides direct connections to SSDs with dedicated pattern generation resources and optimized bus links, enabling full-speed parallel testing and reducing costs by integrating pattern generation and interface logic on a single chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PC-based testers with shared-resource architecture are used, then cost is reduced, but performance and parallelism are limited due to bottlenecks in data transmission
Solution Approach 1:
The system divides the testing architecture into multiple independent configurable ICs, each capable of independently testing one or more DUTs. This segmentation eliminates the shared-resource bottleneck by providing dedicated pattern generation and interface logic for each testing channel, enabling parallel testing without contention for common resources.
Solution Approach 2:
The configurable IC acts as an intermediary device between the control system and the DUTs. It includes dedicated pattern generation resources and interface logic that mediate the data transmission between the controller and multiple storage devices, eliminating the bottleneck of direct PC-based testing while maintaining system manageability.
2Productivity
If PC-based testers are used, then ease of operation is maintained, but parallelism is limited due to shared-resource architecture
Solution Approach 1:
The configurable IC is designed with universal functionality to support multiple interface standards (SATA, SAS, USB, PCIe) and can be programmed to perform different testing functions. This multi-functionality allows a single IC design to handle various DUT types and protocols, simplifying the system while enabling parallel testing of multiple devices with different interface requirements.
Solution Approach 2:
The system employs dynamically reconfigurable ICs that can be programmed via configuration files to adapt to different testing scenarios, interface standards, and DUT types. This dynamic reconfigurability allows the system to maintain ease of operation through software control while achieving high parallelism through hardware acceleration.
3Speed
If dedicated pattern generation resources are implemented, then testing speed is improved, but device complexity increases
Solution Approach 1:
The system replaces software-based pattern generation (mechanical/system-level operation) with hardware-based pattern generation resources implemented in configurable IC logic. This substitution achieves deterministic full-speed testing by performing pattern generation in parallel at the circuit level, eliminating the speed limitations of sequential software processing while the configurable nature keeps the added complexity manageable.
4Speed
If direct connection between configurable IC and DUT is implemented, then data transmission speed is improved, but connection complexity increases
Solution Approach 1:
The configurable IC merges the pattern generation logic, interface protocol handling, and electrical signaling functions into a single integrated device that connects directly to the DUT. This consolidation eliminates intermediate components and buses found in PC-based architectures, achieving full-speed direct connection while the unified design actually reduces overall connection complexity compared to distributed PC-based systems.
Data Source
AI summary
A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmed to provide test patterns and an interface to at least one device under test (DUT). The system also includes a connection to the at least one DUT, wherein the connection is coupled directly between the configurable IC and the at least one DUT.