Configurable IC Register Replacement for Flexible Data Storage
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Solution Overview
Problem
Existing configurable integrated circuits (ICs) lack flexible data storage and passing mechanisms, leading to suboptimal performance due to the limitations of user registers, which often require data to be passed at specific clock edges and increase signal delay.
Innovation Solution
The development of a configurable IC with reconfigurable circuits that define data registers through configurable routing circuits, allowing for flexible data storage and passing operations, and the implementation of user registers using interconnect/storage elements in a master/slave configuration to operate as flip-flops, enabling edge-triggered and double-edge triggered operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If user registers are used for data storage in configurable ICs, then data can be stored and passed between logic circuits, but signal delay increases and flexibility is reduced due to clock edge requirements
Solution Approach 1:
The patent changes the operational parameters of storage elements by allowing them to function in multiple modes (register mode with clocked operation and latch mode with level-sensitive operation). By modifying the enable signal configuration, the same physical circuit can operate differently to optimize for either timing synchronization or speed, thereby reducing signal delay while maintaining data storage capability.
Solution Approach 2:
The patent introduces dynamic configurability where routing circuits can be reconfigured between different operational states. The storage elements dynamically switch between being transparent latches (for fast data passing) and edge-triggered registers (for synchronized data storage) based on control signals, providing adaptability that resolves the contradiction between speed and reliability.
2Reliability
If user registers are used for data storage, then data can be stored between logic circuits, but the circuit complexity increases due to additional control logic
Solution Approach 1:
The patent makes routing circuits universal by enabling them to perform multiple functions: they can act as simple wire interconnects, as transparent latches for fast data transfer, or as edge-triggered registers for synchronized storage. This multi-functionality eliminates the need for separate dedicated register circuits, reducing overall device complexity while maintaining data storage capability.
Solution Approach 2:
The patent merges the interconnect function and storage function into a single configurable routing circuit. By combining these functions, the patent eliminates redundant circuitry and control logic that would exist if separate interconnect and register circuits were used, thereby reducing device complexity while preserving data storage reliability.
3Adaptability or versatility
If configurable routing circuits are used to define data registers, then flexibility in data storage is improved, but the device complexity increases
Solution Approach 1:
The patent employs dynamic reconfiguration capabilities where routing circuits can change their operational characteristics during operation. The same physical routing infrastructure adapts its behavior based on configuration data, providing high versatility without requiring multiple dedicated hardware structures. This dynamic approach achieves adaptability while controlling device complexity through resource sharing.
Data Source
AI summary
Some embodiments provided a method of designing a configurable IC. The method includes receiving a first design that has at least one controllable circuit that is initialized by a first type of initialization signal. This first design also at least one controllable circuit that is initialized by a second type of initialization signal. The method defines a second design based on the first design. The method defines this second design by replacing all controllable circuits that are initialized by the first type of initialization signal with functionally equivalent controllable circuits. Each of these functionally equivalent controllable circuits includes a particular controllable circuit that is initialized by the second type initialization signal.