Configurable Image Processor With Reconfigurable Execution Lanes
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Solution Overview
Problem
Existing image processors are either power-inefficient due to their versatile software-based operations or limited in functionality due to fixed-function hardware, lacking a balance between versatility and power efficiency.
Innovation Solution
A configurable and programmable image processor unit with an array of execution lanes coupled to a two-dimensional shift register array, allowing for efficient processing of image stencils with reduced power consumption and enhanced versatility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based image processing is used on general purpose processors, then versatility is improved, but power consumption increases
Solution Approach 1:
The image processor uses a reconfigurable array of execution elements that can be dynamically programmed to perform different image processing functions. The array elements can be configured through initialization code to implement various algorithms (e.g., convolution, pixel operations), allowing the hardware to adapt its functionality while maintaining efficient parallel processing performance.
Solution Approach 2:
The processor changes its operational parameters by loading different initialization code into the array elements, which modifies the behavior of the execution units. This allows the same physical hardware to perform multiple different image processing tasks by changing the programmed parameters rather than requiring different hardware configurations.
2Use of energy by moving object
If fixed function hardwired circuitry is used, then power consumption is reduced, but versatility is limited
Solution Approach 1:
The image processor implements a universal processing array where each execution element can be programmed to perform multiple different functions. The array elements are designed with configurable parameters and initialization code that enable the same hardware structure to execute various image processing algorithms, making the processor multi-functional rather than dedicated to a single task.
Solution Approach 2:
The processor transitions from static fixed-function circuitry to dynamic reconfigurable hardware. The array elements can be reprogrammed between different operations, allowing the system to adapt its functionality based on the processing requirements while maintaining the power efficiency of hardware-based processing.
3Ease of operation
If finer grained data structures are used in software processing, then programming flexibility is improved, but processing overhead increases
Solution Approach 1:
The patent replaces the software-based instruction fetch and decode mechanism with a hardware-based execution model. Instead of using traditional processor instruction cycles, the system uses directly executable initialization code that configures hardware execution units, eliminating the overhead of instruction decoding and enabling more efficient processing of fine-grained data structures.
Data Source
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AI summary
An image processor unit is described. The image processor unit includes a plurality of inputs to receive at least one input image. The image processor unit includes a plurality of outputs to provide at least one output image. The image processor unit includes a network coupled to the plurality of inputs and the plurality of outputs. The network is to couple at least one of the inputs to at least one of the outputs. The image processor unit includes an image processor circuit coupled to the network. The network to route an input image that is received at one of the inputs to the image processor circuit. The image processor circuit is to execute image signal processing program code to generate a processed output image from the input image. The network is to route the processed output image to at least one of the outputs.