Configurable Interconnect Circuit for Trace Data Routing
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Solution Overview
Problem
In hardware emulation environments, conventional methods require additional logic elements to bypass irrelevant trace data, increasing area and causing timing issues, while only capturing relevant data is desired without bypassing irrelevant data.
Innovation Solution
A configurable interconnect circuit connects relevant trace data from hardware emulator logic elements to a scan chain or trace data storage circuit, selectively routing relevant data for processing while avoiding the need for additional logic elements and bypassing irrelevant data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional logic elements are added to bypass irrelevant trace data in conventional hardware emulators, then the complete trace data can be captured, but the area of data capture circuitry increases and timing issues are introduced
Solution Approach 1:
The patent extracts only the relevant trace data from the hardware emulator by using a trace data filtering mechanism that identifies and captures only the data corresponding to logic gates in the design under test, eliminating the need to capture and bypass irrelevant data from non-corresponding logic elements
Solution Approach 2:
The patent performs preliminary mapping during the synthesis phase where the system pre-identifies which logic elements in the hardware emulator correspond to logic gates in the design under test. This preliminary identification allows the trace capture circuitry to be configured beforehand to capture only relevant data, avoiding the need for additional bypass logic
2Reliability
If additional logic elements are added to bypass irrelevant trace data, then complete trace data is captured, but timing issues are introduced into the circuit
Solution Approach 1:
By extracting only the relevant trace data through pre-configured capture circuitry that targets only corresponding logic elements, the patent eliminates the need for bypass paths that would introduce additional propagation delays and timing constraints
3Loss of information
If trace data is captured from all logic elements, then complete visibility is achieved, but the number of logic elements in data capture circuitry increases
Solution Approach 1:
The patent applies extraction by using a filtering mechanism that identifies and captures only the trace data from logic elements that correspond to logic gates in the design under test, removing the unnecessary capture of data from non-corresponding elements
Solution Approach 2:
During the synthesis phase, the system preliminarily maps the design under test to the hardware emulator and pre-identifies which logic elements correspond to each other, allowing the trace capture circuitry to be configured in advance to capture only relevant data without requiring additional bypass logic
Data Source
AI summary
Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.