Configurable Inversion Stages for Radiation-Hardened Latch Circuits
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Solution Overview
Problem
Radiation-induced external charges pose a significant threat to the security and resiliency of modern computing systems, particularly affecting critical flip-flop circuitry, where existing redundancy measures are difficult to implement due to the vast cell population in small areas.
Innovation Solution
The implementation of a multi-stage latch circuit with configurable inversion stages that filter short duration pulses, allowing them to traverse multiple elements before flipping the logic state, thereby enhancing resilience against radiation-induced errors. This includes logic circuitry with multiple inversion stages that can operate as two-state or tri-state inverters, configured to provide higher resilience against radiation-induced glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional redundancy measures are implemented in memory to combat soft errors, then reliability against radiation is improved, but device complexity and area overhead increase significantly due to vast cell population in small areas
Solution Approach 1:
The patent segments the latch circuit into multiple inversion stages (first inversion logic and second inversion logic) with different transistor configurations. This segmentation allows each stage to be optimized independently for radiation hardness while maintaining overall functionality, reducing the need for extensive redundancy across the entire circuit.
Solution Approach 2:
The patent applies local quality by using different logic configurations (e.g., 4T vs 2T inversion logic) in different stages of the latch circuit. Critical stages that are more susceptible to radiation effects use more robust 4T inversion logic, while less critical stages use simpler 2T logic, optimizing the balance between reliability and complexity locally rather than uniformly across the entire circuit.
2Reliability
If more inversion stages are added to filter radiation-induced glitches, then resilience against radiation is improved, but device area and transistor count increase
Solution Approach 1:
The patent implements dynamic configuration capability where the inversion stages can be selectively enabled or disabled based on operational requirements. This allows the circuit to adapt its complexity and area usage dynamically, using full multi-stage inversion protection only when radiation hardness is critical, while allowing reduced configuration for normal operation to save area.
Solution Approach 2:
The patent changes the parameter of inversion stage configuration by providing multiple logic options (2T vs 4T inversion logic) with different transistor counts and area footprints. This allows selective optimization of area versus reliability by choosing appropriate inversion logic types for different application scenarios.
3Reliability
If configurable inversion logic is implemented to provide radiation hardness, then failure-in-time rate is reduced, but ease of manufacture decreases due to increased configuration complexity
Solution Approach 1:
The patent implements universal inversion logic blocks that can function in multiple modes (2T or 4T configuration) depending on control signals. This multi-functionality allows the same physical circuit structure to provide different levels of radiation hardness without requiring multiple separate circuit designs, simplifying the manufacturing process while maintaining configurability.
Solution Approach 2:
The patent incorporates configuration control logic that is pre-designed and integrated into the latch circuit structure. This preliminary action of embedding control mechanisms during fabrication allows the circuit to be configured for optimal radiation hardness without requiring post-manufacturing modification or complex assembly processes.
Data Source
AI summary
Various implementations described herein are directed to a device having logic circuitry with multiple inversion stages. One or more of the multiple inversion stages may be configured to operate as first inversion logic with a first number of transistors. One or more of the multiple inversion stages may be configured to operate as second inversion logic with a second number of transistors that is greater than the first number of transistors.