Configurable I/O Level Shifter for Multi-Voltage Chip Interfaces
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Solution Overview
Problem
Semiconductor chips face challenges in communicating between different voltage domains, requiring voltage level translation without the practicality of adding additional pins or using on-chip DC-DC converters, which can impact performance and increase chip area.
Innovation Solution
A configurable circuit with parallel data paths and a level shifter that includes a comparator, hysteresis adjusting device, and reference voltage generator, allowing voltage translation between different domains without additional pins or on-chip DC-DC converters, optimizing power consumption and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an additional pin is added to receive a different voltage supply for input/output operations, then voltage level translation is enabled, but chip area increases and manufacturing complexity increases
Solution Approach 1:
The existing I/O pin is designed to perform multiple functions: it can operate in standard mode for single voltage level communication and in level-shifting mode for dual voltage level communication. The configurable circuit enables the same pin to adapt to different voltage domain requirements without requiring additional dedicated pins, thus achieving multi-functionality and eliminating the need for extra chip area.
Solution Approach 2:
The I/O circuit includes an integrated level-shifting mechanism that automatically detects and adapts to voltage level differences. The configurable circuit with parallel data paths and switching mechanism enables the circuit to self-adjust its operation mode based on voltage domain requirements, eliminating the need for external voltage supply pins and reducing chip area.
2Adaptability or versatility
If an on-chip DC-DC converter is used for voltage translation, then voltage level translation is enabled, but power consumption increases and chip area increases
Solution Approach 1:
The invention extracts and removes the DC-DC converter from the chip design, replacing it with an external voltage supply connected through the I/O pin. This eliminates the power-hungry on-chip voltage conversion hardware while maintaining the necessary voltage translation capability through the configurable circuit's switching mechanism, thereby significantly reducing power consumption.
Solution Approach 2:
The I/O pin and configurable circuit act as intermediaries between different voltage domains. Instead of using an on-chip DC-DC converter to actively transform voltage levels, the system uses the I/O pin as a mediator to interface with external voltage supplies, and the configurable circuit to switch between different voltage paths, achieving voltage adaptation without active conversion and reduced power consumption.
3Adaptability or versatility
If a level shifter circuit is implemented, then voltage level translation is enabled, but device complexity increases
Solution Approach 1:
The level-shifting functionality is segmented into distinct parallel data paths, each optimized for specific voltage translation directions (e.g., high-to-low and low-to-high). The configurable switching mechanism selectively activates only the required path based on operating conditions, breaking down the complex voltage translation task into simpler, manageable segments that reduce overall circuit complexity while maintaining adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient voltage level translation between semiconductor chips operating at different voltage levels, reducing static power consumption and die area, while maintaining IO performance without the need for additional pins or on-chip DC-DC converters.
Implementation Method 1
The first path may include a resistor divider
Data Source
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AI summary
A circuit (200) for translating a voltage of a digital signal (Input) from a first voltage level (Outside 200) of a first voltage domain to a second voltage level (Vx) of a second voltage domain (Vdd) is disclosed. The circuit includes a configurable circuit (226) to be coupled between the first voltage domain (outside 200) and the second voltage domain (Vdd). The configurable circuit includes a plurality of parallel data paths (P1, P2, P3), wherein the configurable circuit is configured to enable only one of the plurality of data paths at a given time. A first path (P1) in the plurality of parallel data paths is configured to be enabled (216 closed) when the first voltage level (Vpin) is greater than the second voltage level (Vdd) and a second path (P3) in the plurality of data parallel data paths is configured to be enabled when the first voltage level (Vpin) is lesser than the second voltage level (Vdd).