Configurable LDPC Decoder Memory Layout for Low-Latency Parallel Decoding
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Solution Overview
Problem
Existing LDPC decoders face inefficiencies in processing large and sparse parity check matrices, leading to increased storage requirements and latency due to the need to access and store data across multiple memory locations, which can cause conflicts and reduce decoding performance.
Innovation Solution
A configurable LDPC decoder architecture that utilizes multiple independently addressable memories and check node processing systems to process soft decision data in parallel, allowing for a wider memory width than the product of the number of check nodes and bit node data width, enabling simultaneous access to complete check node blocks without storing unnecessary data, thus reducing latency and improving throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple memory locations are used to store soft decision data for LDPC decoding, then the decoder can handle large and sparse parity check matrices, but storage requirements increase and latency increases due to conflicts
Solution Approach 1:
The parity check matrix is divided into sub-matrices, and the soft decision data is segmented into check node blocks that can be processed independently. This segmentation allows the decoder to handle large matrices by processing smaller blocks sequentially, reducing the amount of data that needs to be stored in memory at any one time.
Solution Approach 2:
The decoder pre-loads check node blocks into memory before processing begins. By preparing the data in advance and organizing it into manageable blocks, the system minimizes the need for random memory access during decoding, thereby reducing latency and memory conflict issues.
2Productivity
If multiple memory locations are used to store soft decision data, then the decoder can process LDPC codes, but latency increases due to the need to access and store data across multiple memory locations
Solution Approach 1:
The soft decision data is divided into check node blocks corresponding to sub-matrices of the parity check matrix. Each block can be processed independently by dedicated check node processing systems, enabling parallel processing that reduces overall decoding latency while maintaining the ability to handle large LDPC codes.
Solution Approach 2:
The decoder architecture introduces a temporal dimension by processing check node blocks sequentially through multiple decoding passes. Instead of accessing all memory locations simultaneously, the system processes data in organized passes, which reduces memory access conflicts and latency.
3Speed
If memory width is increased to store complete check node blocks, then simultaneous access is enabled, but storage requirements increase
Solution Approach 1:
The memory is organized to store check node blocks that correspond to sub-matrices of the parity check matrix. By segmenting the storage into these logical blocks, the decoder can access complete check node blocks simultaneously when needed, while the total storage requirement is managed by processing data in sequential passes rather than loading the entire matrix at once.
Data Source
AI summary
Methods and apparatus for decoding LDPC codes provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. In an embodiment, a configurable LDPC decoder, which supports many different LDPC codes having any sub-matrix size, comprises several independently addressable memories which are used to store soft decision data for each bit node. The decoder further comprises a number, P, of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P≥PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.