Configurable Level Shifter Circuit for Multi-Voltage I/O
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Solution Overview
Problem
Semiconductor chips face challenges in communicating data between different voltage domains without the practicality of adding additional pins, as existing solutions like on-chip DC-DC converters consume more space and impact IO performance.
Innovation Solution
A configurable circuit with parallel data paths and a level shifter circuit, including a comparator and hysteresis adjusting device, enables voltage translation between different voltage domains without requiring an additional pin or on-chip DC-DC converter, optimizing space and IO performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an additional pin is added to receive a different voltage supply, then voltage level translation between different voltage domains is enabled, but chip pin count increases and fabrication complexity worsens
Solution Approach 1:
The existing I/O pin is made multi-functional by integrating voltage level translation capability into the existing pin structure. The pin serves both as a general-purpose I/O and as a voltage domain interface, eliminating the need for dedicated voltage selection pins while maintaining adaptability to different voltage domains through internal circuit switching
2Adaptability or versatility
If an on-chip DC-DC converter is used for voltage translation, then voltage level adaptation is achieved, but chip area increases and IO performance is impacted
Solution Approach 1:
The voltage translation function is extracted from the bulky DC-DC converter architecture and implemented through a streamlined path selection circuit that switches between existing on-chip voltage domains. This removes the need for large converter circuits while retaining voltage adaptation capability, significantly reducing the required chip area
Solution Approach 2:
A path selection circuit acts as an intermediary between different voltage domains, routing signals through appropriate voltage translation paths without requiring direct DC-DC conversion. This mediator approach enables voltage domain crossing using existing voltage domains and minimal additional circuitry, avoiding the area penalty of full converters
3Device complexity
If a simple voltage divider is used for voltage translation, then circuit complexity is reduced, but power consumption increases and translation precision is compromised
Solution Approach 1:
The circuit dynamically selects between different translation paths based on the operating voltage domain. The path selection circuit adjusts the active translation mechanism in real-time, enabling the system to use more efficient paths when available and fallback to simpler paths only when necessary, thereby optimizing power consumption while maintaining translation capability across varying voltage conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively translates voltage levels between chips operating at different voltages, ensuring valid data recognition without additional pins or space-consuming converters, while minimizing power consumption and maintaining IO performance.
Implementation Method 1
The first path may include a resistor divider
Implementation Method 2
the level shifter circuit includes a comparator, which is formed by an input differential transistor pair with a matched current mirror load
Implementation Method 3
a hysteresis adjusting device, a parallel signal path circuit and a reference voltage generator. The comparator and the hysteresis adjusting device set transition thresholds and hysteresis of the level shifter
Data Source
AI summary
A circuit for translating a voltage of a digital signal from a first voltage level of a first voltage domain to a second voltage level of a second voltage domain is disclosed. The circuit includes a configurable circuit to be coupled between the first voltage domain and the second voltage domain. The configurable circuit includes a plurality of parallel data paths, wherein the configurable circuit is configured to enable only one of the plurality of data paths at a given time. A first path in the plurality of parallel data paths is configured to be enabled when the first voltage level is greater than the second voltage level and a second path in the plurality of parallel data paths is configured to be enabled when the first voltage level is lesser than the second voltage level.