Configurable Locked-Loop Circuit for Stable PLL Frequency Control
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Solution Overview
Problem
Existing phase-locked loop (PLL) circuits are often not configurable or reconfigurable, making them difficult to integrate with flexible circuitry like FPGAs and requiring fixed IC layouts, which limits their use across various frequency ranges, jitter levels, power consumption, and temperature variations.
Innovation Solution
A reconfigurable, digital phase-locked loop that generates a frequency reference or delay with phase detection, allowing for configuration of parameters such as frequency, bandwidth, jitter level, and power consumption, and can be integrated into any IC design with a variable layout, using a circuitry netlist and standard cells of any silicon fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed IC layout (floorplan) is used for PLL circuits, then manufacturing and integration are simplified, but adaptability to different frequency ranges, jitter levels, and power consumption requirements is reduced
Solution Approach 1:
The patent implements dynamic configurability in the PLL circuit by allowing the floorplan to be reconfigured for different operating conditions. The circuit can dynamically adjust its layout and parameters based on frequency range, jitter level, and power consumption requirements, transforming a static design into an adaptive system that optimizes performance for various applications.
Solution Approach 2:
The invention enables parameter changes in the PLL circuit by providing configurable options for frequency range, bandwidth, jitter level, and power consumption. These parameter changes are achieved through reconfigurable circuit elements and control mechanisms that allow the same hardware to operate across multiple specifications without requiring fixed manufacturing constraints.
2Adaptability or versatility
If PLL circuits are made configurable for multiple parameters, then adaptability and versatility improve, but device complexity increases
Solution Approach 1:
The patent achieves multi-functionality by designing a universal PLL circuit architecture that can perform multiple functions across different frequency ranges and operating conditions. The same circuit core handles various configurations for frequency, bandwidth, jitter, and power consumption, eliminating the need for separate dedicated circuits for each function and thereby managing complexity through consolidation.
Solution Approach 2:
The invention applies segmentation by dividing the PLL circuit into reconfigurable modules or stages that can be independently configured. This modular approach allows complex configurability to be managed through discrete, manageable segments that can be tuned individually, reducing the perceived complexity while maintaining overall adaptability.
3Ease of manufacture
If a black box PLL design with predetermined layout is used, then ease of manufacture is improved, but ease of operation and integration into custom IC designs is reduced
Solution Approach 1:
The patent transforms the static black box design into a dynamic system where the layout and configuration can be adjusted during operation and integration. The PLL circuit responds to control inputs that modify its behavior and physical arrangement, enabling seamless integration into custom IC designs while maintaining manufacturing simplicity through standardized interfaces.
4Speed
If PLL circuits are designed for high frequency ranges, then speed and performance improve, but stability and accuracy decrease due to PVT variations
Solution Approach 1:
The patent implements feedback mechanisms that continuously monitor and adjust the PLL circuit parameters to compensate for PVT variations at high frequencies. The feedback loop detects frequency drift caused by process, voltage, and temperature changes and applies corrective adjustments, maintaining both high speed performance and frequency stability simultaneously.
Solution Approach 2:
The invention utilizes parameter changes to adapt the circuit behavior for high-frequency operation. By dynamically adjusting parameters such as bandwidth, gain, and timing constants based on operating conditions, the circuit maintains stability and accuracy even when operating at elevated frequencies where PVT variations have greater impact.
Data Source
AI summary
A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.