Configurable Logic Analyzer Circuit for Debugging
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Solution Overview
Problem
Current in-circuit debugging methods are limited by fixed signal selection and probe depth, which restrict the number of signals that can be monitored and the duration of sampling, requiring redesign and re-implementation of the circuit to change these parameters, thus delaying the debugging process.
Innovation Solution
A system that allows dynamic adjustment of signal selection and probe depth without modifying the circuit design, using a logic analyzer circuit coupled to a programmable integrated circuit, where a debugger program enables selection of probe signals and trigger logic, and remaps on-chip memory to accommodate changing parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed signal selection and probe depth are used in in-circuit debugging, then the circuit implementation is simplified, but the debugging flexibility and adaptability are reduced
Solution Approach 1:
The patent implements dynamic signal selection and probe depth configuration through programmable logic devices and configurable memory structures. The logic analyzer circuit can be reconfigured at runtime to select different signals and adjust sampling depth without hardware changes, resolving the contradiction between debugging flexibility and circuit complexity by making the system adaptable through software/control signals rather than fixed hardware design.
Solution Approach 2:
The patent enables parameter changes in signal selection and probe depth through configurable control mechanisms. The boundary scan interface and on-chip memory allow dynamic modification of which signals are monitored and how deeply they are sampled, permitting debugging parameters to be adjusted without redesigning the circuit architecture.
2Measurement precision
If the number of monitored signals and sampling duration are increased, then the diagnostic capability is improved, but the memory requirements and circuit complexity increase
Solution Approach 1:
The patent segments the memory structure into multiple banks or regions that can be independently configured for different signal groups. This segmentation allows efficient utilization of memory resources by allocating specific memory portions to specific signals, enabling increased diagnostic capability without proportionally increasing total memory requirements.
Solution Approach 2:
The patent implements universal memory structures that can serve multiple functions - storing data from different signals, supporting various probe depths, and accommodating different debugging scenarios. The same memory infrastructure is reused across multiple debugging configurations, reducing the need for dedicated memory resources for each diagnostic function.
3Adaptability or versatility
If the circuit is redesigned to change debugging parameters, then the debugging adaptability is improved, but the time required for debugging is increased
Solution Approach 1:
The patent implements preliminary configuration capabilities where debugging parameters such as signal selection and probe depth can be set up in advance through programmable logic and control structures. This preliminary setup eliminates the need for time-consuming circuit redesign when parameter changes are needed during debugging sessions.
Solution Approach 2:
The patent introduces a boundary scan interface and control logic as intermediaries between the debugging tools and the circuit-under-test. This intermediary layer enables parameter changes to be applied through software or control signals without requiring physical circuit redesign, significantly reducing the time needed to adapt debugging parameters.
Data Source
AI summary
Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.