Configurable Logic Gate Array for Circuit ECO Timing
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Solution Overview
Problem
Conventional circuit design faces challenges in efficiently addressing engineering change orders (ECOs) due to the need for connecting standard spare elements, which can cause timing violations and increase signal transmission paths, especially when these elements are not located near the circuit path that needs modification.
Innovation Solution
The method involves designing circuits with configurable logic gate array cells that can replace specific elements in the path, determining timing margins, and selectively changing the metal layer connections to alter the function of these cells, allowing for functional replacement without increasing signal path length and reducing the risk of timing violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard spare elements are placed in remaining chip space during circuit design, then the circuit function can be changed after receiving ECO, but the signal transmission path increases significantly causing timing violation
Solution Approach 1:
The patent applies preliminary action by pre-placing configurable logic gate array cells at multiple candidate locations within the circuit path during the initial design phase. These cells are configured to match the original element's function, so when an ECO is received, the replacement can be done immediately without adding long connection paths, thus avoiding timing violations while maintaining adaptability.
2Adaptability or versatility
If standard spare elements are used for ECO, then functional replacement is achieved, but additional connection lines are required increasing device complexity
Solution Approach 1:
The patent implements universality by designing configurable logic gate array cells that can be programmed to perform multiple different logic functions. Instead of placing dedicated spare elements for each possible replacement scenario, a single configurable cell can replace different elements (AND gate, OR gate, buffer, etc.) by changing its configuration, thereby reducing the number of physical connection lines needed while maintaining high adaptability for ECOs.
Data Source
AI summary
A circuit design method is provided, including the steps of: designing a plurality of paths, wherein each path includes a plurality of elements; determining a specific path of the plurality of paths by performing a timing analysis; replacing the specific element in the specific path with the configurable logic gate array cell; and selectively changing a connection mode of a metal layer to make the configurable logic gate array cell have another function. The timing analysis includes: for each path of the plurality of paths, determining whether a chip area meets a constraint condition and whether a timing violation will occur when a specific element in each path is replaced with a configurable logic gate array cell; and when both conditions are met, determining that path as the specific path.