Configurable Logic Gate Blocks for Underused Hard IP Resources

The patent implements logic gate circuit blocks that can function as universal logic units, capable of performing multiple logic functions (AND, OR, NOT, NAND, NOR, XOR, etc.) by configuring their internal logic gates. These blocks serve as alternatives to hard IP blocks, allowing the same physical resources to be used for different logic functions based on configuration, thereby eliminating resource waste when hard IP blocks are underutilized.

The patent introduces dynamically reconfigurable logic gate circuit blocks that can change their functionality through configuration data loaded into memory elements. This dynamic reconfiguration capability allows the circuit to adapt to different computational tasks, providing flexibility comparable to soft logic while maintaining the structured approach of hard logic, thus optimizing resource utilization.

The patent merges hard IP blocks with logic gate circuit blocks in a hybrid architecture where both types of blocks coexist and can be selectively used. The logic gate circuit blocks are integrated into the fabric alongside hard IP blocks, sharing common routing resources. This merging allows the circuit to leverage the high performance of hard IP blocks when needed while using the flexible logic gate blocks for other functions, increasing overall logic density without proportionally increasing complexity.

The patent introduces multiplexers as intermediary components that select between outputs from hard IP blocks and logic gate circuit blocks. These multiplexers act as mediators that manage the complexity of the hybrid architecture by providing a unified interface to the routing fabric, allowing selective activation of either hard or soft logic paths without requiring complex control logic throughout the entire circuit.