Configurable Logic Slices With Dual LUTs for Area and Power Limits

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Solution Overview

Problem

Existing programmable logic devices face challenges in achieving high functionality with reduced area and power consumption, particularly in implementing complex logic operations using a fraction of the hardware and with lower power consumption.

Innovation Solution

The introduction of configurable logic slices, each comprising a first and second lookup table (LUT) and a two-to-one multiplexer, allowing for flexible configuration modes such as S44, S45, and S55 to enhance functionality while optimizing area and power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If complex LUT structures are used to implement functionality, then functionality is improved, but area and power consumption increase

Engineering Contradiction:
ImprovefunctionalityVSAvoidhardware area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The logic slice is divided into two separate LUTs (LUT1 and LUT2) with distinct functionality. LUT1 implements first logic functions and LUT2 implements second logic functions, allowing independent optimization of each unit's area while achieving complex overall functionality through their combination and interconnection via the multiplexer and routing resources.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If complex LUT structures are used to implement functionality, then functionality is improved, but power consumption increases

Engineering Contradiction:
ImprovefunctionalityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The logic slice is divided into two separate LUTs (LUT1 and LUT2) with distinct functionality. LUT1 implements first logic functions and LUT2 implements second logic functions, allowing independent optimization of each unit's area while achieving complex overall functionality through their combination and interconnection via the multiplexer and routing resources.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The multiplexer dynamically selects between the output of LUT1 and LUT2 based on configuration, allowing the logic slice to adapt its functionality at runtime. This dynamic selection enables the same hardware structure to implement different logic functions without requiring additional permanent circuitry, reducing overall power consumption.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If more hardware resources are allocated to logic blocks, then functionality is improved, but area increases

Engineering Contradiction:
ImprovefunctionalityVSAvoidhardware area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

Each LUT is designed to implement multiple logic functions through programmable lookup tables. LUT1 can implement various first logic functions and LUT2 can implement various second logic functions, allowing the same physical hardware to serve multiple logical purposes. The multiplexer further enhances universality by enabling the output to come from either LUT1 or LUT2 based on configuration, maximizing functionality without proportionally increasing area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250337414A1Configurable logic slices for programmable logic devices
Publication Date: 2025.10.30 LATTICE SEMICON CORP
  • US20250337414A1 patent drawing
  • US20250337414A1 patent drawing
  • US20250337414A1 patent drawing

AI summary

Configurable logic slices for programmable logic devices and methods of using and programming such logic slices and devices are presented herein. In one embodiment, a programmable logic device (PLD) is disclosed that includes a logic slice. The logic slice may include a first look-up table (LUT) configured to generate a first output; and an input switch stage configured to receive the first output and selectively generate a first signal. The logic slice may further include a second LUT configured to receive the first signal and to generate a second output; and a two-to-one multiplexer configured to receive the first output and the second output and selectively produce an output of the logic slice.