Configurable Logic Slices for Larger LUT Functions With Less Area
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Solution Overview
Problem
Existing programmable logic devices face challenges in implementing complex logic functions with reduced hardware usage and lower power consumption, particularly in achieving the functionality of complex LUT structures while minimizing area and power consumption.
Innovation Solution
The introduction of configurable logic slices comprising a first LUT, an input switch stage, a second LUT, and a two-to-one multiplexer, which can be configured to generate outputs equivalent to a 6-input or 7-input LUT, allowing for flexible logic configurations and reduced resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex LUT structures are used to implement logic functions, then functionality is improved, but hardware area and power consumption increase
Solution Approach 1:
The patent divides a complex LUT structure into multiple smaller LUTs (e.g., two 4-input LUTs instead of one 6-input or 7-input LUT). Each smaller LUT handles a portion of the logic function, and their outputs are combined through multiplexing. This segmentation reduces the area required for each individual LUT while maintaining the overall functionality through coordinated operation of multiple smaller units.
Solution Approach 2:
The patent implements a hierarchical structure where smaller LUTs are nested within a larger logic slice framework. The logic slice contains multiple LUTs that can be configured to work together, with multiplexers selecting between different LUT outputs. This nested arrangement allows complex logic functions to be built from simpler, reusable building blocks, reducing total hardware area.
2Adaptability or versatility
If complex LUT structures are used to implement logic functions, then functionality is improved, but power consumption increases
Solution Approach 1:
By segmenting complex LUT functions into multiple smaller LUTs, the patent reduces the switching activity and power consumption associated with large LUT structures. Each smaller LUT operates independently with lower power requirements, and the overall power consumption is reduced compared to implementing the same function in a single large LUT.
Solution Approach 2:
The patent introduces multiplexers that dynamically select between outputs of different LUTs based on configuration. This dynamic switching capability allows the logic slice to adapt to different logic functions without requiring a fixed large LUT structure, enabling power-efficient implementation by activating only the necessary LUTs for each specific function.
3Area of stationary object
If smaller LUT structures are used, then hardware area is reduced, but functionality is limited
Solution Approach 1:
The patent combines multiple smaller LUTs within a logic slice to achieve the functionality of larger LUTs. By merging the outputs of several 4-input LUTs through multiplexers and logic circuits, the system can implement complex 6-input or 7-input logic functions while using only smaller, more area-efficient LUT building blocks.
Solution Approach 2:
The logic slice design creates a universal building block that can implement multiple different logic functions using the same smaller LUT structures. Through configurable multiplexers and interconnections, the same physical hardware can be programmed to perform various logic functions, providing adaptability without requiring dedicated large LUTs for each function.
Data Source
AI summary
Configurable logic slices for programmable logic devices and methods of using and programming such logic slices and devices are presented. In an exemplary aspect, a method of programming a programmable logic device (PLD) is presented, wherein the PLD provides a plurality of available lookup table (LUT) structures. In some embodiments, the method includes mapping a logic design to a selected LUT of a plurality of LUTs of different numbers of inputs, wherein the selected LUT has an associated LUT equation; and mapping the selected LUT to a first LUT structure from the plurality of available LUT structures based on the associated LUT equation.