Configurable Mailbox Data Buffer for Asynchronous Core Communication

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Solution Overview

Problem

Multi-processor core microcontrollers face challenges in efficiently and reliably communicating small amounts of data across clock boundaries between cores with different system clocks, requiring a fully configurable and silicon-efficient communication interface.

Innovation Solution

A single chip microcontroller design featuring a master core and slave core with a communication interface that includes configurable directional data registers, flow control logic, and handshake signals, allowing for programmable data direction and assignment to mailboxes, along with optional FIFO memory for efficient data transfer between asynchronous clock domains.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a communication interface is designed to be fully configurable for data transfer between cores, then adaptability is improved, but device complexity increases

Engineering Contradiction:

Improveconfigurability of communication interfaceVSAvoidcomplexity of communication interface

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The communication interface is segmented into multiple independent data registers (e.g., MBXD0-MBXD15) that can be individually configured. Each register can be independently assigned to different mailboxes and configured for specific data directions, allowing the system to be customized for particular applications without increasing overall structural complexity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The data registers are designed with multi-functionality, serving as universal building blocks that can be assigned to different mailboxes and configured for various data transfer scenarios. The same register structure can handle different data directions (master-to-slave, slave-to-master) and be assigned to different mailbox numbers, providing adaptability without requiring separate dedicated structures for each function

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If data registers are made configurable with programmable directions, then adaptability is improved, but manufacturing complexity increases

Engineering Contradiction:

Improveprogrammable data directionVSAvoidmanufacturing configurability

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The data register configuration is established through fuse programming during the manufacturing process. The fuse bits (e.g., cfg_mbox_master_data_rd[n]) are pre-configured to define the data direction and mailbox assignment for each register before the device is shipped. This preliminary configuration action allows the device to be customized for specific applications during manufacturing without adding operational complexity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The configurability is achieved by changing the state of fuse bits during manufacturing. By programming different combinations of fuse bits, the same physical register structure can be configured with different data directions (master read/write, slave read-only, etc.) and assigned to different mailbox numbers, providing manufacturing flexibility through simple binary parameter changes

Inventive Principle:

Principle #35Parameter changes

3Reliability

If flow control logic is added to ensure reliable data transfer across clock boundaries, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvereliability of data transferVSAvoidcomplexity of flow control logic

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Flow control logic acts as an intermediary mechanism between the master and slave cores. The handshake signals (e.g., DTRDY flags in status registers) mediate the data transfer process by indicating when data is ready to be read or written. This intermediary flow control ensures reliable data transfer across asynchronous clock boundaries without requiring complex synchronization protocols or additional buffering structures

Inventive Principle:

Principle #24Intermediary (Mediator)

4Adaptability or versatility

If multiple configurable data registers are implemented for mailbox communication, then adaptability is improved, but silicon usage increases

Engineering Contradiction:

Improvenumber of configurable registersVSAvoidsilicon usage

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

Multiple data registers are merged into a unified configurable structure that shares common control logic and configuration mechanisms. The registers MBXD0-MBXD15 form a consolidated array that can be collectively configured through a systematic fuse programming approach, reducing the overhead of having completely separate configuration structures for each register and optimizing silicon utilization

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10120815B2Configurable mailbox data buffer apparatus

Publication Date: 2018.11.06 MICROCHIP TECHNOLOGY INC

AI summary

A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.