Configurable Memory Module Address Control Connections
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Solution Overview
Problem
Conventional Dual Inline Memory Modules (DIMMs) have a fixed ratio of address and data transfers, limiting data throughput when applications require different access granularities, as the pin-out fixes the ratio of address and data transfers, leading to suboptimal performance in accessing memory with lower granularity.
Innovation Solution
A memory module with configurable address and control connections, allowing grouping into N sets for N separatively controllable groups of memory chips, enabling flexible configuration of address and data transfers to match specific application needs without altering mechanical or electrical properties, thus allowing customers to choose between higher data transaction rates and larger data granularity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the pin-out of conventional DIMM is used, then the mechanical and electrical properties are fixed, but the ratio of address transfers and data transfers is fixed, limiting data throughput for lower granularity access
Solution Approach 1:
The patent applies dynamics by making the connection grouping configurable rather than fixed. The memory module allows dynamic reconfiguration of address and control connections into N sets, enabling the system to adapt the ratio of address transfers to data transfers based on application requirements. This resolves the contradiction by allowing adaptability in memory access granularity while maintaining a fixed physical pin-out structure.
Solution Approach 2:
The patent changes the parameter of connection grouping configuration. By allowing the pin-out to be configured into different numbers of sets (N sets of address and control connections), the system can adjust the ratio of address transfers to data transfers. This parameter change enables optimization for different memory access granularities without altering the physical mechanical or electrical properties of the DIMM.
2Ease of operation
If data is accessed with lower granularity, then more fine-grained data access is enabled, but the data throughput decreases because the access rate is limited by the address wires
Solution Approach 1:
The patent applies segmentation by dividing the address and control connections into N separate sets. Each set can be independently configured to work with specific groups of memory chips. This segmentation allows the system to provide more address wires effectively by distributing them across multiple sets, thereby enabling lower granularity access while maintaining or improving data throughput through parallel access capabilities.
Solution Approach 2:
The patent introduces another dimension by organizing connections into multiple sets that can be separatively controlled. Instead of a single fixed address bus, the system uses N sets of address and control connections that can be independently activated. This dimensional change allows simultaneous or alternating access to different memory chip groups, effectively increasing the address transfer capacity and maintaining data throughput even with lower granularity access patterns.
3Productivity
If the number of connections is increased to support higher data throughput, then data transfer capacity improves, but the mechanical and electrical constraints of the DIMM are exceeded
Solution Approach 1:
The patent applies universality by making the existing connections multi-functional through configurable grouping. The same physical connections can be configured into different numbers of sets (N sets) depending on the application requirements. This allows the system to achieve variable data throughput and memory access patterns without adding more physical connections, thereby maintaining data transfer capacity within the mechanical and electrical constraints of the DIMM.
Data Source
AI summary
The memory module having a plurality of memory chips and a plurality of connections for connecting the memory module to a processor. At least part of the connections is configurable to be grouped into N sets of address and control connections for N separatively controllable groups of memory chips of the plurality of memory chips (N≧2).