Configurable Memory Architecture for SoC Domain Allocation
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Solution Overview
Problem
Current system memory configurations in embedded processing devices, such as SoCs, often fail to meet the varying and sometimes competing memory requirements of real-time and application domains, leading to underutilization of resources and performance issues due to differing latency and bandwidth needs.
Innovation Solution
A dynamic memory architecture with a memory manager that allocates floating memory blocks among different bus masters or domains based on specific requirements, allowing for configuration during startup or restart, and maintaining data coherency, thus eliminating the need for hardware or software changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If system memory is split between real-time and application domains with fixed configurations, then each domain can have dedicated memory resources, but resource utilization is suboptimal and cannot adapt to varying application requirements
Solution Approach 1:
The patent implements dynamic memory allocation where the memory manager can reconfigure which memory blocks are assigned to real-time or application domains based on runtime requirements. This allows the system to adapt memory distribution to varying workloads without requiring fixed hardware configurations, resolving the contradiction between adaptability and complexity by making the allocation policy flexible while keeping the physical architecture simple.
Solution Approach 2:
The memory manager serves multiple functions: it manages memory allocation for both domains, handles arbitration for shared memory blocks, and provides configuration flexibility. This multi-functional approach consolidates complexity into a single management component rather than requiring separate dedicated memory controllers for each domain, improving adaptability while controlling overall system complexity.
2Adaptability or versatility
If additional RAM is included in fixed configuration to meet peak requirements, then sufficient resources are available for maximum functionality, but surplus components remain unutilized in other configurations
Solution Approach 1:
The system dynamically allocates memory blocks to domains based on actual runtime requirements rather than providing fixed maximum capacity. The memory manager can allocate fewer blocks when application domain needs are low, allowing the system to adapt to varying workloads and avoid energy waste from unused memory capacity, while still having the ability to expand when needed.
3Speed
If high latency pipelined interconnect is used for memory access, then system bandwidth can be increased, but real-time processing capability is degraded due to access throttling
Solution Approach 1:
The patent segments memory into separate blocks that can be dedicated to either real-time or application domains. By partitioning memory rather than using a unified shared memory space, the system can provide dedicated low-latency memory paths for real-time domain while maintaining high bandwidth capabilities for application domain through separate memory blocks, eliminating the throttling problem of shared pipelined access.
4Quantity of substance
If shared memory is used between domains, then memory resources are efficiently utilized, but performance degradation occurs due to arbitration overhead and latency variations
Solution Approach 1:
The memory system is segmented into dedicated blocks for each domain with optional shared blocks. This segmentation allows most memory accesses to occur within domain-specific blocks without arbitration overhead, while shared blocks provide efficient resource utilization when both domains need access. This resolves the contradiction by combining the benefits of dedicated memory (performance consistency) and shared memory (resource efficiency) in a hierarchical structure.
Data Source
Figure 1
Figure 2
AI summary
An integrated circuit (IC) includes a memory manager (116) having a plurality of memory ports (117), each configured to communicate with a corresponding floating memory block (122,124,126,128,130,132,134,136). The IC includes a first interconnect (103, 105) for a first domain, wherein the first interconnect has a first set of fixed ports (103) configured to communicate with memory blocks (114) dedicated to the first domain and a first set of floating ports (105) configured to communicate with the memory manager (116), and a second interconnect (109, 111) for a second domain, wherein the second interconnect has a second set of fixed ports (111) configured to communicate with memory blocks (120) dedicated to the second domain and a second set of floating ports (109) configured to communicate with the memory manager (116). The memory manager (116) is configured to allocate a first portion of the memory ports (117) to the first set of floating ports (110) and a second portion of the memory ports (117) to the second set of floating ports (109).