Configurable Memory ECC for SECDED Without Die Size Growth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices, particularly DRAM, face challenges in maintaining data integrity due to errors introduced during storage and retrieval, with existing error correction mechanisms either failing to correct double-bit errors accurately or inadvertently introducing additional errors.
Innovation Solution
The implementation of configurable error correction modes within memory devices, allowing for selective operation between Single Error Correction (SEC) and Single Error Correction Double Error Detection (SECDED) modes, using additional circuitry to adapt SEC circuitry for SECDED operations without increasing die size, and adjusting error detection codeword granularity to enhance error detection and correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SECDED mode is implemented to correct double-bit errors, then reliability is improved, but existing methods may inadvertently introduce additional errors
Solution Approach 1:
The patent implements dynamic error correction by configuring the memory device to switch between SEC and SECDED modes based on operational requirements. The controller receives configuration commands to selectively enable SECDED mode for enhanced double-bit error correction or SEC mode for standard operation, allowing the system to adapt its error correction capability dynamically rather than being fixed in one mode.
Solution Approach 2:
The patent changes the operational parameters of the error correction circuitry by adjusting the granularity of error detection codewords. In SECDED mode, the system modifies how codewords are structured and processed to enable detection of double-bit errors while maintaining the correction of single-bit errors. This parameter adjustment allows the same hardware to perform different error correction functions without introducing additional errors.
2Reliability
If SECDED circuitry is added to enable double error detection, then reliability is improved, but device complexity and die size increase
Solution Approach 1:
The patent makes the existing SEC circuitry multi-functional by configuring it to operate in both SEC mode and SECDED mode. The same error correction circuitry that originally handled single-bit errors is now capable of detecting double-bit errors when configured in SECDED mode. This eliminates the need for separate dedicated SECDED circuitry, thereby avoiding increases in device complexity and die size while still providing enhanced error detection capability.
Solution Approach 2:
The patent introduces dynamic configurability to the ECC system, allowing the controller to receive commands that switch the error correction mode between SEC and SECDED. This dynamic configuration enables the system to activate advanced error detection capabilities only when needed, rather than having permanent complex circuitry always present, thus maintaining simplicity in normal operation while providing enhanced reliability when required.
3Reliability
If error correction operations are performed on all data, then reliability is improved, but processing time increases
Solution Approach 1:
The patent applies partial error correction action by implementing SECDED mode selectively rather than continuously. The controller determines when to enable SECDED operations based on configuration commands, applying enhanced error correction only to specific data operations that require it. This partial application of error correction maintains data integrity for critical operations while avoiding the time penalty of universal SECDED processing for all data.
Solution Approach 2:
The patent implements dynamic error correction timing by allowing the system to switch between SEC and SECDED modes based on operational requirements. When SECDED mode is enabled, error correction is performed with enhanced capability; when in SEC mode, standard error correction is used. This dynamic approach allows the system to optimize processing time by using the simpler SEC mode for routine operations while providing enhanced protection when needed.
Data Source
AI summary
Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.