Configurable Memory Interleaving for Uniform Channel Distribution
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Solution Overview
Problem
Conventional memory interleaving techniques are not scalable, inefficient, and lack uniformity across multiple memory channels, particularly for three-way interleaving, leading to wasteful use of resources and hardware inefficiencies.
Innovation Solution
A method of iterative address bit mapping across memory channels, where each round selects a unique subset of address bits to achieve uniform distribution, with the last round using most significant bits to ensure all channels are evenly mapped, adhering to the equation N=(L−K)/F, where N is the number of channels, L is the maximum unique combinations, and F is the number of mappings per channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional memory interleaving techniques are used for three-way interleaving, then uniform distribution across memory channels is achieved, but hardware complexity and resource wastage increase
Solution Approach 1:
The patent segments the address bits into different groups that are mapped to different memory channels in a systematic pattern. By dividing the address space and applying different mapping rules to different bit segments, the patent achieves uniform distribution across channels without requiring complex hardware logic. The segmentation of address bits allows simple combinational logic to achieve what would otherwise require complex control mechanisms.
Solution Approach 2:
The patent introduces dynamic configurability to the interleaving scheme, allowing the system to adapt to different numbers of memory channels and interleaving patterns. This dynamic approach enables the same hardware structure to be reconfigured for various interleaving scenarios (2-way, 3-way, 4-way, etc.) without requiring dedicated hardware for each configuration, thereby reducing overall hardware complexity while maintaining uniform distribution.
2Productivity
If a wider data bus is used to access all three memory channels simultaneously, then memory access bandwidth is improved, but power consumption and area increase
Solution Approach 1:
The patent implements periodic action by systematically cycling through different memory channels in a round-robin fashion based on address bit patterns. Instead of activating all channels simultaneously (which would require a wide data bus and high power), the interleaving scheme periodically switches between channels in a predictable pattern, achieving high aggregate bandwidth through time-multiplexed access while keeping power consumption low by activating only one channel at a time.
3Adaptability or versatility
If conventional interleaving schemes are used for non-power-of-2 channel counts, then scalability is limited, but adapting to arbitrary channel numbers requires complex remapping
Solution Approach 1:
The patent creates a universal interleaving scheme that can handle any number of memory channels (not just powers of 2) using the same fundamental hardware structure. The mapping logic is designed to be channel-count agnostic, allowing the system to scale from 2-way to 3-way to 4-way interleaving and beyond without requiring different hardware architectures. This universality is achieved through a systematic approach to address bit mapping that naturally adapts to any channel count.
Solution Approach 2:
The patent utilizes parameter changes by allowing the interleaving configuration to be adjusted through simple parameter settings rather than hardware redesign. By changing parameters such as the number of channels and the specific bit mapping patterns, the system can adapt to different interleaving requirements. This parameter-based configurability enables scalability to arbitrary channel counts while keeping the underlying hardware structure simple and unchanged.
Data Source
AI summary
A method of interleaving a memory by mapping address bits of the memory to a number N of memory channels iteratively in successive rounds, wherein in each round except the last round: selecting a unique subset of address bits, determining a maximum number (L) of unique combinations possible based on the selected subset of address bits, mapping combinations to the N memory channels a maximum number of times (F) possible where each of the N memory channels gets mapped to an equal number of combinations, and if and when a number of combinations remain (K, which is less than N) that cannot be mapped, one to each of the N memory channels, entering a next round. In the last round, mapping remaining most significant address bits, not used in the subsets in prior rounds, to each of the N memory channels.