Configurable Memory Modules for High-Speed Channel Capacity
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Solution Overview
Problem
The number of memory modules that can be connected to a single channel in memory systems has decreased with increased signaling rates, leading to degraded signaling integrity and limited signal rates due to increased load on the channels.
Innovation Solution
The implementation of a configurable, variable-data-width memory module and alternative motherboard wiring patterns that allow each channel of a memory controller to communicate with up to four modules, with each DQ link group connecting to at most two memory modules, thereby reducing the load on data link groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more memory modules are connected to a single channel, then storage capacity increases, but signaling integrity degrades and signal rates are limited
Solution Approach 1:
The data link is segmented into multiple independent DQ link groups, where each group connects to a subset of memory modules. This segmentation isolates the load on each link group, allowing more modules to be connected to the channel without degrading signaling integrity on individual link groups.
Solution Approach 2:
The patent transitions from a single broad data bus to a multi-dimensional architecture with multiple DQ link groups and data link groups. This dimensional expansion allows parallel communication paths, increasing the number of modules per channel while maintaining signal integrity through distributed connectivity.
2Quantity of substance
If more memory modules are connected to a single channel, then storage capacity increases, but signal rates are limited
Solution Approach 1:
The channel is divided into multiple DQ link groups that can operate independently at high signal rates. By segmenting the connection, each link group handles fewer modules, preserving signal rate performance while the aggregate capacity across all link groups increases.
Solution Approach 2:
The patent implements configurable data widths and dynamic routing capabilities that allow the system to adapt signal paths based on operational requirements. This dynamic configuration enables optimal signal rates by routing signals through paths with appropriate loading characteristics.
3Quantity of substance
If each DQ link group connects to more memory modules, then channel capacity increases, but load on data link groups increases and signaling integrity degrades
Solution Approach 1:
The patent segments the data link into multiple DQ link groups, each with a controlled number of connected modules. This segmentation distributes the load across multiple smaller groups rather than concentrating it on fewer overloaded groups, maintaining signaling integrity while increasing total channel capacity.
Solution Approach 2:
The architecture provides universal connectivity where multiple DQ link groups can serve multiple memory modules through a unified control structure. This multi-functional design allows the same data link infrastructure to support varying numbers of modules while maintaining optimal loading through configurable routing.
Data Source
AI summary
Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.