Configurable Memory Device for Multi-Mode Operation

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Solution Overview

Problem

There is a need for memory devices that can operate in multiple modes to reduce component count and complexity in electronic systems while maintaining functionality, as existing systems require multiple types of devices to perform various functions.

Innovation Solution

A memory device configured to operate in multiple modes, including user data storage, programmable logic device (PLD), content addressable memory (CAM), and neural network modes, by utilizing a controller that can switch between these modes and allocate memory array partitions accordingly, allowing it to perform functions previously handled by separate peripheral devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple types of devices (processors, logic circuitry, memory) are used to provide various functions in electronic systems, then functionality and processing capability are improved, but component count and system complexity increase

Engineering Contradiction:
ImprovefunctionalityVSAvoidcomponent count
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory device is designed to perform multiple functions beyond traditional data storage, including content addressable memory operations, pattern matching, data processing, and logic operations. The same memory array and control circuitry are utilized to execute different operational modes, allowing a single device to replace multiple specialized components in electronic systems.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines previously separate devices (memory devices, content addressable memory, pattern matching devices, and data processing devices) into a single integrated memory device. The control circuitry is enhanced to support multiple operational modes, merging the functionality of multiple discrete components into one unified device that reduces system complexity and component count.

Inventive Principle:
Principle #5Merging (Combining)

2Device complexity

If traditional memory devices are used solely for data storage, then device simplicity is maintained, but processing capability and adaptability are limited

Engineering Contradiction:
Improvedevice simplicityVSAvoidprocessing capability
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The memory device incorporates dynamic operational modes that allow it to switch between different functional states based on operational requirements. The control circuitry can configure the memory array to operate in various modes including standard data storage, content addressable memory operations, pattern matching, and data processing, enabling the device to adapt its functionality dynamically rather than being fixed in a single mode.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10712960B2Configurable operating mode memory device and methods of operation
Publication Date: 2020.07.14 MICRON TECHNOLOGY INC
  • US10712960B2 patent drawing
  • US10712960B2 patent drawing
  • US10712960B2 patent drawing

AI summary

Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.