Configurable Memory Pool for OpenFlow Packet Processing

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Solution Overview

Problem

OpenFlow's existing architecture and protocol face limitations in efficiently processing network packets, particularly in handling wide packet header vectors and managing match and action operations across multiple tables, leading to inefficiencies in memory usage and processing speed.

Innovation Solution

A packet processing block with a configurable pool of unit memories that can operate as either match or action memories, allowing flexible allocation and usage for match, action, statistics, and meter operations, enhancing the OpenFlow switch's ability to handle wide packet headers and improve processing efficiency by optimizing memory utilization and processing speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate dedicated memories are allocated for match and action operations in OpenFlow switches, then each operation has dedicated storage capacity, but memory resource utilization efficiency deteriorates and overhead increases

Engineering Contradiction:
Improvematch and action operation reliabilityVSAvoidmemory resource utilization efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements a universal memory pool where memory units can be dynamically configured to serve either match operations or action operations. Each memory unit in the pool is designed with configurable functionality, allowing the same physical memory resource to fulfill different operational roles based on real-time requirements, thereby eliminating the need for separate dedicated memories while maintaining operational reliability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system employs dynamic memory allocation and configuration mechanisms that allow memory units to be reassigned between match and action functions based on changing operational demands. This dynamic reconfigurability ensures that memory resources are optimally utilized at any given time while maintaining the reliability needed for both match and action operations

Inventive Principle:
Principle #15Dynamics

2Device complexity

If fixed memory allocation is used for match and action tables, then memory management is simplified, but adaptability to different packet header widths and operation requirements deteriorates

Engineering Contradiction:
Improvememory management complexityVSAvoidadaptability to packet header width
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The memory pool is divided into multiple independent memory units that can be individually configured and allocated. This segmentation allows the system to adapt to different packet header widths by selectively activating and configuring the appropriate number and type of memory units, while the centralized pool management keeps overall complexity manageable

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each memory unit in the pool is designed with universal functionality, capable of operating as either match memory or action memory. This universality enables the system to adapt to varying packet header widths and operation requirements by reconfiguring the same physical memory resources without requiring separate dedicated memory structures for each scenario

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If traditional OpenFlow architecture processes wide packet header vectors, then comprehensive packet inspection is achieved, but processing speed deteriorates due to inefficiencies in memory access and operation handling

Engineering Contradiction:
Improvepacket header inspection completenessVSAvoidpacket processing speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent merges the previously separate match and action memory structures into a unified memory pool. This consolidation eliminates redundant memory access operations and reduces the time required to switch between match and action operations, thereby improving packet processing speed while maintaining the ability to perform comprehensive packet header inspection through the configurable memory units

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10979353B2Packet processing match and action unit with configurable memory allocation
Publication Date: 2021.04.13 TEXAS INSTRUMENTS INC
  • US10979353B2 patent drawing
  • US10979353B2 patent drawing
  • US10979353B2 patent drawing

AI summary

A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.