Configurable Memory Trace Buffers for Cycle-Accurate Access Capture

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Solution Overview

Problem

Existing memory tracing methods require special purpose hardware and cannot capture cycle-accurate memory access patterns without disrupting the system or changing the workload, limiting their effectiveness in real-world production environments.

Innovation Solution

A configurable circuitry system that captures memory access patterns for configurable time durations, storing trace data including read/write accesses, addresses, and timestamps, which can be encrypted and compressed, and operates within a disaggregated memory pool, allowing analysis of memory device utilization without disrupting the system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If special purpose hardware is used for memory tracing, then memory access patterns can be captured, but the system is disrupted and workload must be changed

Engineering Contradiction:
Improvememory access pattern capture accuracyVSAvoidsystem integrity
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent introduces a trace buffer as an intermediary component that captures memory access patterns without directly interfering with the memory operation path. The trace buffer receives copies of address signals and control signals from the memory interface, allowing accurate tracing while maintaining normal memory operations. This intermediary approach resolves the contradiction by enabling measurement without disruption.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the memory system into distinct functional components: the main memory operation path and the separate tracing path. The tracing functionality is divided into address capture logic, control signal capture logic, and trace buffer storage, operating independently from the primary memory access path. This segmentation allows precise measurement while preserving system reliability.

Inventive Principle:
Principle #1Segmentation

2Loss of information

If existing memory tracing methods are used, then some memory access information can be obtained, but cycle-accurate patterns cannot be captured without system disruption

Engineering Contradiction:
Improvememory access information completenessVSAvoidtracing system complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent creates a universal tracing interface that can capture multiple types of memory access information (read/write commands, addresses, control signals) through a single integrated trace buffer system. The same trace buffer infrastructure handles different tracing requirements by configuring what signals are captured, rather than requiring separate specialized hardware for each tracing function. This reduces device complexity while maintaining information completeness.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If memory tracing is implemented in production environment, then real-world memory patterns can be captured, but special purpose hardware is required

Engineering Contradiction:
Improveproduction environment compatibilityVSAvoidhardware requirements
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the tracing functionality with existing memory controller components. The trace buffer and capture logic are integrated into the memory controller's existing signal routing and control structures, rather than adding completely separate special-purpose hardware. This integration allows production environment deployment using modified existing hardware rather than requiring entirely new specialized tracing equipment.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12455821B2Memory access tracing
Publication Date: 2025.10.28 INTEL CORP
  • US12455821B2 patent drawing
  • US12455821B2 patent drawing
  • US12455821B2 patent drawing

AI summary

Examples described herein relate to circuitry, when operational, configured to: store records of memory accesses to a memory device by at least one requester based on a configuration, wherein the configuration is to specify a duration of memory access capture. In some examples, the at least one requester comprises one or more workloads running on one or more processors. In some examples, the configuration is to specify collection of one or more of: physical address ranges or read or write access type.