Configurable Multiplexing Circuitry for Memory Arrays
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Solution Overview
Problem
Conventional memory architecture designs face inefficiencies in multiplexing logic, particularly when expanding to higher orders of multiplexing operations, making it difficult to achieve high-performance multiplexing operations due to limitations in responding to delays and failures.
Innovation Solution
The implementation of selectively configurable and scalable multiplexing schemes that allow for flexible multiplexer options within memory macros, enabling expansion from mux4 to mux8 or mux16 while maintaining consistent logic depth and timing, and coupling redundant Q outputs to logic zero to avoid floating outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional multiplexing logic is used in memory architecture, then the design is simple and easy to manufacture, but the multiplexing operations become inefficient when expanding to higher orders
Solution Approach 1:
The multiplexing logic is divided into multiple independent multiplexer blocks (e.g., four separate mux4 units) that can be configured to work individually or in combination. This segmentation allows the system to achieve higher-order multiplexing (mux8, mux16) by combining multiple simpler units rather than using a single complex multiplexer, thereby maintaining manufacturing simplicity while improving productivity.
Solution Approach 2:
The multiplexer blocks are designed with universal functionality to support multiple multiplexing orders (mux4, mux8, mux16) and various configuration modes. Each multiplexer block can be configured to serve different purposes depending on the application requirements, allowing a single design to handle multiple functions without requiring separate dedicated circuits for each multiplexing order.
2Reliability
If conventional memory designs are used, then the design responds to specific delays and failures, but high performance multiplexing operations are difficult to achieve
Solution Approach 1:
The multiplexer configuration is made dynamic and reconfigurable, allowing the system to adapt to different timing requirements and failure conditions. The multiplexer blocks can be dynamically configured to change their operation modes based on real-time needs, enabling the system to respond to delays and failures while maintaining high performance multiplexing operations.
Solution Approach 2:
The system allows for parameter changes in the multiplexer configuration, such as changing the number of active multiplexer blocks, adjusting selection signals, and modifying operational modes. These parameter changes enable the system to optimize its response to delays and failures while maintaining high performance multiplexing operations.
3Quantity of substance
If multiplexing logic is expanded to higher orders, then more data can be processed, but the logic depth and timing become inconsistent
Solution Approach 1:
The multiplexing logic is segmented into multiple identical multiplexer blocks with consistent internal structure. Each block has the same logic depth and timing characteristics, which ensures that when multiple blocks are combined to achieve higher-order multiplexing, the overall system maintains consistent timing and logic depth. This segmentation approach allows for scalable data processing capacity while preserving manufacturing precision.
Solution Approach 2:
The patent introduces a new dimension of configuration where multiple multiplexer blocks can be arranged in parallel or series configurations to achieve different multiplexing orders. By organizing the multiplexer blocks in a structured dimensional arrangement, the system can scale data processing capacity while maintaining consistent logic depth and timing across all blocks.
Data Source
AI summary
Various implementations described herein are related to a device having memory circuitry having an array of memory cells. The device may include output circuitry coupled to the memory circuitry, and the output circuitry may have a first set of multiplexers that receives column data from the array of memory cells and provides first multiplexed output data. The device may include output interface circuitry coupled to the output circuitry, and the output interface circuitry may have a second set of multiplexers that receives the first multiplexed output data from the output circuitry and selectively provides second multiplexed output data based on a configurable mode of multiplexed operation.