Configurable Multiplier Array for Dual-Mode Floating-Point Arithmetic
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Solution Overview
Problem
Existing logic circuitry designed for 32-bit floating-point operations is inefficient when used for 16-bit floating-point operations, as it requires padding and inefficient use of resources.
Innovation Solution
A dual-mode logic circuitry system that can operate in both 32-bit and 16-bit floating-point modes, using recoding terms and a configurable multiplier array to generate partial products for either one 32-bit or two 16-bit results, allowing for efficient processing in different operating modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic circuitry designed for 32-bit floating-point operations is used to perform 16-bit floating-point operations by padding with zeros, then compatibility with IEEE floating-point standards is maintained, but processing efficiency deteriorates
Solution Approach 1:
The logic circuitry is designed with dynamic reconfigurability, allowing it to switch between 32-bit and 16-bit floating-point operation modes. The circuit can dynamically adjust its internal structure and resource allocation based on the operating mode, enabling efficient processing for each specific precision requirement without being locked into a fixed configuration
Solution Approach 2:
The invention changes the operational parameters of the logic circuitry by implementing different recoding schemes for mantissas based on the operating mode. For 16-bit operations, a specialized recoding approach is applied that optimizes the partial product generation process, thereby improving processing efficiency while maintaining IEEE standard compliance
2Measurement precision
If logic circuitry is designed to perform 32-bit floating-point operations, then high precision processing capability is achieved, but resource utilization deteriorates when performing 16-bit operations
Solution Approach 1:
The logic circuitry is segmented into functional blocks that can be independently configured for different operation modes. The multiplier array and associated logic are divided into segments that can be activated or deactivated based on whether 32-bit or 16-bit operations are being performed, reducing resource consumption when full precision is not required
Solution Approach 2:
The logic circuitry is designed with multi-functionality to handle both 32-bit and 16-bit floating-point operations efficiently. By implementing mode-specific recoding and partial product generation strategies, the same hardware resources can be universally applied to different precision requirements without waste, achieving both high precision capability and efficient resource utilization
Data Source
AI summary
A system and method are provided for performing 32-bit or dual 16-bit floating-point arithmetic operations using logic circuitry. An operating mode that specifies an operating mode for a multiplication operation is received, where the operating mode is one of a 32-bit floating-point mode and a dual 16-bit floating-point mode. Based on the operating mode, nine recoding terms for a mantissa of at least one floating-point input operand are determined. A dual-mode multiplier array circuit that is configurable to generate partial products for either one 32-bit floating-point result or for two 16-bit floating-point results computes the partial products based on the nine recoding terms. The partial products are processed to generate an output based on the operating mode.