Selectively Configurable PHY Interface for NAND and 3D XPoint Memory
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Solution Overview
Problem
Current high-speed non-volatile memory systems are limited as they can only support either NAND or 3D XPoint memory devices due to the need for separate physical layer (PHY) interfaces, leading to wasted resources and increased costs due to unused PHY interfaces and IO pin inefficiencies.
Innovation Solution
A selectively configurable PHY interface that can communicate with both NAND and 3D XPoint memory devices, integrated into a single apparatus with memory controllers and a multiplexer, allowing for flexible pin assignment and configuration to support multiple types of memory devices, reducing the need for separate PHY interfaces and optimizing IO pin usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate PHY interfaces are used for NAND and 3D XPoint memory devices, then each memory type can be supported with dedicated optimization, but device complexity increases and IO pin efficiency decreases
Solution Approach 1:
The patent implements a single PHY interface that can be selectively configured to support both NAND and 3D XPoint memory devices. The interface includes configurable parameters such as data width, clock frequency, and signal timing that can be adjusted via control registers to match the specific requirements of either memory type. This universal approach eliminates the need for separate dedicated PHY interfaces while maintaining full compatibility with both memory standards.
Solution Approach 2:
The PHY interface employs dynamic reconfiguration capabilities where interface parameters can be changed at runtime based on the detected memory type. The system includes a memory type detection mechanism that automatically configures the PHY interface parameters appropriately when a memory device is connected, allowing the same physical interface to adapt its electrical characteristics and signaling behavior to match the connected device's requirements.
2Reliability
If separate PHY interfaces are implemented for different memory types, then each interface can be optimized for its specific memory type, but manufacturing cost increases due to wasted layout space and unused components
Solution Approach 1:
The patent merges the functionality of separate NAND PHY and 3D XPoint PHY interfaces into a single unified PHY interface structure. This consolidation combines the electrical interface circuits, control logic, and configuration mechanisms into one integrated block, reducing the overall silicon area required and eliminating redundant components. The unified design maintains all necessary optimization capabilities for both memory types while significantly reducing manufacturing costs through improved layout efficiency.
3Device complexity
If a single configurable PHY interface is used for both memory types, then device complexity is reduced and manufacturing cost decreases, but the difficulty of detecting and measuring the correct configuration increases
Solution Approach 1:
The patent implements a memory type detection mechanism that performs preliminary identification of the connected memory device before full operation begins. The system uses initial signaling sequences and response analysis to detect whether a NAND or 3D XPoint device is connected, then automatically configures the PHY interface parameters accordingly. This preliminary detection action prevents configuration errors and simplifies the overall system operation by automating the setup process.
Data Source
AI summary
An apparatus includes: a first memory controller that corresponds with a first type of non-volatile memory device; a second memory controller that corresponds to a second type of non-volatile memory device, wherein the second type of non-volatile memory device is different from the first type of non-volatile memory device; an physical layer (PHY) interface; and an interface controller coupled to the PHY interface for controlling signal transmission by the PHY interface; wherein the PHY interface is selectively configurable or is user-configured to allow the PHY interface to communicate with one or more memory devices belonging to the first type, the second type, or both.