Configurable Pin Resources for Multi-Interface ICs

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Solution Overview

Problem

Conventional integrated circuit devices require distinct off-chip pins for each interface, limiting flexibility and increasing costs due to the need for different die configurations for varying system requirements, as the number of pins needed for each interface varies between different systems.

Innovation Solution

Implementing a configurable pin resource system that allows off-chip pins to be dynamically reconfigured to serve as connections to memory, network, or other I/O interfaces based on bandwidth requirements, enabling a single design to be fabricated for multiple systems and allowing pins to be repurposed in the field to match changing interface demands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If distinct off-chip pins are allocated for each interface (memory controller, network interface controller), then each interface can operate independently and reliably, but the number of off-chip pins increases and flexibility decreases

Engineering Contradiction:
Improveinterface operation reliabilityVSAvoidpin configuration flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The off-chip pins are designed to serve multiple interfaces through a pin distribution mechanism. The same physical pin can be dynamically assigned to different interfaces (memory controller or network interface controller) based on system configuration requirements, enabling one pin to perform multiple functions rather than requiring dedicated pins for each interface

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If more off-chip pins are provided for additional interfaces, then interface functionality is enhanced, but manufacturing costs increase and device complexity rises

Engineering Contradiction:
Improveinterface functionalityVSAvoidpin distribution complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The pin distribution mechanism merges the pin resources of multiple interfaces into a shared pool. Instead of maintaining separate dedicated pin sets for memory controller and network interface controller, the system combines them into a unified configurable pin resource that can be dynamically allocated, reducing the total number of pins required while maintaining full interface functionality

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If dedicated pins are assigned to each interface, then signal integrity is maintained, but power consumption increases due to more active pins

Engineering Contradiction:
Improvesignal integrityVSAvoidstatic power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The pin assignment is made dynamic rather than static. The pin distribution mechanism allows pins to be reconfigured between different interfaces based on operational requirements. When an interface is not active, its assigned pins can be deactivated or reassigned, reducing the number of continuously active pins and thereby lowering static power consumption while maintaining signal integrity during active operation

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9886409B2System and method for configuring a channel
Publication Date: 2018.02.06 NVIDIA CORP
  • US9886409B2 patent drawing
  • US9886409B2 patent drawing
  • US9886409B2 patent drawing

AI summary

An integrated circuit device comprises pin resources, a memory controller circuit, a network interface controller circuit, and transmitter circuitry. The pin resources comprise pads coupled to off-chip pins of the integrated circuit device. The memory controller circuit comprises a first interface and the network interface controller circuit comprises a second interface. The transmitter circuitry is configurable to selectively couple either a first signal of the first interface or a second signal of the second interface to a first pad of the pin resources based on a pin distribution between the first interface and the second interface.