Configurable Processor Pipeline for Error Detection Mode
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Solution Overview
Problem
Existing data processing systems face inefficiencies in error detection and correction, particularly in processor pipelines, where error correction code (ECC) modes require additional cycles for partial writes and affect execution timing, while parity modes may not provide sufficient error detection for safety-critical applications.
Innovation Solution
A data processing system capable of operating in either parity or ECC mode, allowing for partial writes with multiple accesses in ECC mode and full writes with a single access, and configuring the processor pipeline differently based on the mode to optimize execution timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC mode is used for error detection and correction, then reliability is improved, but productivity deteriorates due to additional cycles required for partial writes
Solution Approach 1:
The system dynamically configures the instruction pipeline based on the error detection mode (parity or ECC). When ECC mode is selected, the pipeline is configured to handle the additional error correction operations. When parity mode is selected, the pipeline uses a simpler configuration. This dynamic adaptation allows the system to optimize for either reliability or productivity depending on the operational requirements.
Solution Approach 2:
The invention changes the pipeline configuration parameters based on the selected error detection mode. Different pipeline stages are enabled or disabled depending on whether parity or ECC mode is active. This parameter change allows the system to adjust its operational characteristics to match the required error detection level, thereby resolving the contradiction between reliability and productivity.
2Reliability
If ECC mode is used for full writes, then reliability is improved, but device complexity increases due to multiple access requirements
Solution Approach 1:
The instruction pipeline is segmented into multiple stages, with specific stages dedicated to error detection and correction operations in ECC mode. By dividing the pipeline into distinct functional segments, the system can handle complex ECC operations without overwhelming the overall device complexity. Each segment performs a specific function, making the complex error correction process more manageable and efficient.
3Reliability
If different error detection schemes are used, then reliability is improved, but productivity deteriorates due to different execution timings in processor instruction pipeline
Solution Approach 1:
The instruction pipeline is designed with multi-functionality to support both parity and ECC error detection schemes. The same pipeline infrastructure can operate in different configurations depending on the selected error detection mode. This universal design allows the system to maintain consistent productivity characteristics across different error detection schemes while still providing the reliability benefits of both parity and ECC modes.
Data Source
AI summary
A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.