Configurable Pipeline Processor for Parallel Dataflow Reconfiguration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional CPUs and GPUs are inflexible in their hardware configurations, making it difficult to achieve high-degree parallel processing and streamline data flow for repetitive computational tasks like signal processing, navigation, and machine learning, as they lack the flexibility to reconfigure data paths between memory, register files, and ALUs.
Innovation Solution
A programmable data processor with multiple stream processors interconnected by configurable interconnection elements, including arithmetic and logic operator circuits, building block circuits, and a control circuit, allowing for customizable execution pipelines and synchronization through a barrier controller, with periodic timing signals and gating circuits to manage data flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional CPUs or GPUs are used with fixed hardware configurations, then the processor structure is simple and reliable, but the adaptability to reconfigure data paths for different computational tasks is poor
Solution Approach 1:
The patent implements dynamic reconfigurability by allowing the data paths between memory, register files, and ALUs to be dynamically changed based on computational task requirements. The processor architecture includes configurable interconnection elements that can be reconfigured to create different data flow paths, enabling adaptation to various computational patterns without hardware changes.
Solution Approach 2:
The processor is divided into multiple stream processors interconnected by configurable interconnection elements. Each stream processor contains configurable pipeline circuits with arithmetic and logic operator circuits that can be independently configured. This segmentation allows flexible reconfiguration of data paths between individual processing units while maintaining overall system functionality.
2Productivity
If numerous repetitive computational operations are performed using conventional instruction sequences, then the computational capability is sufficient, but the parallel processing efficiency is low due to fixed data flow paths
Solution Approach 1:
The patent enables continuous computational operations by creating execution pipelines where results from one arithmetic or logic operator circuit are directly fed as operands to the next operator circuit in the pipeline. This eliminates the need for repeated memory fetch and write back operations, allowing repetitive computational tasks to be performed continuously with high parallel efficiency.
Solution Approach 2:
The processor architecture pre-configures multiple data paths and execution pipelines that can be selected and activated based on the computational task. The configurable interconnection elements and pipeline circuits are prepared in advance to support different computational patterns, enabling rapid switching between efficient data flow paths without time-consuming reconfiguration during execution.
3Adaptability or versatility
If the data paths between memory, register files and ALUs are made reconfigurable, then the adaptability for different computational tasks is improved, but the device complexity increases
Solution Approach 1:
The configurable interconnection elements and pipeline circuits are designed to serve multiple functions across different computational tasks. The same reconfigurable data path infrastructure supports various arithmetic operations, data flow patterns, and computational algorithms, eliminating the need for separate dedicated paths for each function and reducing overall system complexity.
Solution Approach 2:
The processor uses parameter-based configuration where the behavior and connectivity of data paths are controlled by configurable parameters stored in control circuits. By changing these parameters, the data paths can be reconfigured for different tasks without physical hardware changes. This parameter-driven approach simplifies the control logic compared to hardwired reconfiguration mechanisms.
Data Source
AI summary
A programmable data processor includes multiple numerous configurable pipeline circuits each including numerous arithmetic and logic operator circuits that can be configured into an execution pipeline that can be controlled according to a state machine. Each configurable pipeline circuit also includes numerous building block circuits that can configured into a sequencer for the state machine. The building block circuits may include (i) state elements for representing a state in the state machine, and (ii) loop elements for representing a loop in the state machine.