Configurable PLL Switching Between Analog and Hybrid Digital Loops
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Solution Overview
Problem
Conventional phase-locked loops (PLLs) face limitations in combining the advantages of both analog and digital loops, leading to a need for a configurable PLL that can operate effectively in both analog and hybrid analog-digital modes.
Innovation Solution
A phase-locked loop device that includes a switching mechanism to configure the circuit between an analog mode with a phase detector, analog loop filter, and voltage-controlled oscillator, and a digital mode with a phase detector, time-to-digital converter, digital loop filter, and digital-to-analog converter, allowing for seamless switching between the two modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional PLL uses only analog components, then the circuit is simple and easy to manufacture, but it cannot effectively reduce noise and spurs in digital signal processing applications
Solution Approach 1:
The PLL circuit dynamically switches between analog and digital modes based on operational requirements. The controller selectively enables or disables digital components (TDC, digital loop filter, DAC) to transform the circuit from a static analog design to a dynamic hybrid system that adapts to different signal processing needs, effectively reducing noise and spurs when digital mode is activated.
Solution Approach 2:
The invention changes the operational parameters of the PLL by switching between two distinct configurations: analog mode for simplicity and digital mode for enhanced noise filtering. The controller adjusts the state of digital components to alter the circuit's filtering characteristics, enabling effective suppression of noise and spurs in digital signal processing applications while maintaining analog-like simplicity when needed.
2Object-affected harmful factors
If a conventional PLL uses only digital components, then noise and spurs are reduced, but the device complexity increases and manufacturing becomes more difficult
Solution Approach 1:
The PLL employs dynamic switching between analog and digital operational modes. The controller activates digital components (TDC, digital loop filter, DAC) only when digital signal processing is required, transforming the circuit from a permanently complex digital design to a dynamic hybrid system that maintains analog simplicity during analog operations while providing digital noise filtering when needed.
Solution Approach 2:
The PLL circuit is designed with multi-functionality to handle both analog and digital signal processing requirements. By integrating optional digital components that can be selectively enabled or disabled, the circuit serves dual purposes: simple analog frequency synthesis when digital components are disabled, and enhanced noise-filtered digital signal processing when they are activated, thereby reducing overall device complexity while maintaining versatility.
3Adaptability or versatility
If a PLL is designed to be configurable between analog and digital modes, then adaptability is improved, but the device complexity increases due to additional switching mechanisms
Solution Approach 1:
The PLL implements dynamic mode switching through a controller that selectively enables or disables digital components based on operational requirements. This dynamic approach allows the circuit to transition between analog and digital modes without requiring complex permanent dual-path architecture, achieving high adaptability while keeping the switching mechanism relatively simple through selective component activation rather than parallel redundant paths.
Solution Approach 2:
The PLL circuit achieves multi-functionality by designing a hybrid architecture where digital components (TDC, digital loop filter, DAC) are integrated but selectively activated. This universal design allows the same circuit to perform both analog frequency synthesis and digital signal processing with noise filtering, improving adaptability while avoiding the complexity of maintaining completely separate analog and digital circuits by using shared components with selective activation.
Data Source
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AI summary
A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.