Configurable Pointer Register for Arbitrary Bit Packing
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Solution Overview
Problem
Existing microprocessor systems face inefficiencies in storing and loading data with non-power-of-two bit lengths, requiring software-based solutions that are not suitable for fast operations and often necessitate hardware modifications, which are undesirable.
Innovation Solution
A microprocessor system with a hardware extension that allows for configurable bit lengths per data element during packing and unpacking operations, enabling efficient storage and loading of data with arbitrary bit lengths without altering the processor-memory interface, using a single instruction to combine operations and reduce processor load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If software-based packing and unpacking operations are used for non-power-of-two bit lengths, then memory space is saved, but processing speed deteriorates
Solution Approach 1:
The patent replaces software-based bit manipulation operations with dedicated hardware circuitry including bit extraction logic, packing logic, and unpacking logic. This hardware implementation performs parallel bit operations simultaneously, eliminating the sequential processing delays inherent in software solutions while achieving efficient memory space utilization through configurable bit-width packing.
Solution Approach 2:
The patent introduces intermediate registers and buffer structures that hold data elements during the packing and unpacking processes. These intermediary elements enable seamless data transformation between different bit representations without requiring full software intervention, thus maintaining high processing speed while achieving compact memory storage.
2Productivity
If hardware modifications are made to support arbitrary bit lengths, then processing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent employs configurable control signals and dynamic parameter settings that allow the hardware to adapt to different bit lengths without requiring physical reconfiguration. The packing and unpacking operations can be dynamically adjusted through control registers, enabling the same hardware structure to handle various data formats efficiently while maintaining manageable complexity.
Solution Approach 2:
The patent designs universal packing and unpacking circuits that can handle multiple bit lengths (8, 16, 32, 64 bits) using the same hardware infrastructure. This multi-functional approach eliminates the need for separate dedicated circuits for each bit width, thereby improving processing efficiency across different data types while avoiding the complexity multiplication that would result from multiple specialized hardware components.
3Device complexity
If fixed power-of-two bit lengths are used for data elements, then hardware simplicity is maintained, but memory space efficiency deteriorates
Solution Approach 1:
The patent changes the parameter of data element bit length from fixed power-of-two values to configurable arbitrary values. By introducing control mechanisms that specify the actual bit length required for each data element, the system achieves efficient memory space utilization by packing only the necessary bits while maintaining relatively simple hardware through reusable packing and unpacking circuits.
Solution Approach 2:
The patent segments the data processing function into distinct packing and unpacking stages with configurable parameters. This segmentation allows the hardware to process different bit lengths efficiently by dividing the operation into manageable steps: extracting the required number of bits, packing them into compact representations for storage, and unpacking them back to original format for processing, thereby achieving memory efficiency without proportionally increasing hardware complexity.
Data Source
AI summary
A microprocessor system includes a processing circuit and a memory operably coupled to the processing circuit and configured to receive input data according to a pack and store operation and output the data according to a load and unpack operation. The processing circuit comprises a hardware extension configured to: configure a variable number of bits per data element during a pack and store operation; store a concatenation of a plurality of data elements with a reduced number of bits; extract a plurality of data elements with a reduced number of bits during a load and unpacking operation; and recreate a plurality of data elements with an increased number of bits per data element representative of the data elements prior to the pack and store operation.