Configurable Ready Busy Control for Memory Systems
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Solution Overview
Problem
In memory systems, a single ready/busy signal line cannot provide sufficient information about the condition of individual integrated circuits when multiple chips share the same line, making it difficult for the controller to determine which chip is busy or ready, leading to increased complexity and cost.
Innovation Solution
A memory control system that uses a busy control register to configure the ready/busy signal, allowing the controller to selectively mask or unmask signals from individual chips, enabling the transmission of specific busy status over a shared line, and automatically switching signals based on chip selection, thereby providing detailed status information without additional controller intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple integrated circuits share a single ready/busy signal line, then the number of signal lines is reduced, but the controller cannot determine which specific chip is busy or ready
Solution Approach 1:
The patent segments the ready/busy status information by introducing a chip selection mechanism. Each integrated circuit is assigned a unique chip select signal, and the ready/busy status is segmented to correspond with specific chip selections. This allows the controller to determine which specific chip is busy or ready by combining the chip select signal with the ready/busy signal, resolving the information loss problem while maintaining a shared signal line.
2Device complexity
If a single ready/busy line is used to represent conditions of multiple memory units, then the signal line count is reduced, but additional information about individual chip conditions cannot be provided
Solution Approach 1:
The patent adds another dimension to the signal representation by introducing the chip select signal as a separate dimension. Instead of trying to encode all chip status information in a single ready/busy line, the system uses two dimensions: chip select signals to identify which chip is being addressed, and the ready/busy signal to indicate the status of that specific chip. This dimensional approach allows versatile information representation while keeping the signal line count low.
3Loss of information
If individual ready/busy lines are provided for each integrated circuit, then complete status information is available, but the complexity and cost of the system increases
Solution Approach 1:
The patent merges the ready/busy signal lines from multiple integrated circuits into a single shared line. By combining multiple individual ready/busy lines into one shared resource and using chip select signals to differentiate between chips, the system reduces the total number of signal lines required while maintaining the ability to monitor the status of each individual chip, thereby reducing system complexity and cost.
Data Source
AI summary
A memory unit has a busy control system that includes a busy control register that may be written by a controller. The contents of the busy control register determine whether a signal is sent from the memory unit to the controller and, if so, which of a plurality of signals is sent. A signal may automatically be sent from a selected memory unit and masked from an unselected unit.