Configurable Register Circuitry for Timing Error Detection
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Solution Overview
Problem
Integrated circuits face performance slowdown due to timing variability, leading to overly pessimistic timing requirements and slow clock rates, as they struggle to handle manufacturing and environmental variations effectively.
Innovation Solution
The implementation of configurable register circuitry with error detection and error correction capabilities, allowing the circuit to operate as conventional registers or registers with error detection and correction, enabling higher clock rates in timing variability tolerant designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing guard bands are added to account for manufacturing and environmental variations, then reliability is improved, but clock rate decreases
Solution Approach 1:
The patent applies preliminary action by capturing signals at two different times (using two registers triggered by the same clock edge) before the timing fault can affect the output. This proactive dual-capture mechanism allows the system to detect and correct timing variations before they propagate, enabling higher clock rates without sacrificing reliability
Solution Approach 2:
The patent implements feedback through the XOR comparator that continuously compares the two captured signals and generates an error detection signal. This feedback mechanism allows the system to identify timing faults and activate correction logic, replacing the need for conservative timing guard bands with an active error detection and correction system
2Reliability
If error detection and correction circuitry is added, then timing fault tolerance is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the single register function into two separate registers (first and second registers) that operate in parallel. This segmentation allows independent capture of signals at different time points, enabling error detection through comparison while maintaining modular circuit architecture that manages complexity
Solution Approach 2:
The patent implements multi-functionality by designing the register circuitry to operate in multiple modes: normal mode (single register operation), error detection mode (dual register comparison), and error correction mode (automatic correction via multiplexer selection). This universal design allows the same circuit structure to provide both standard register functionality and enhanced error tolerance
Data Source
AI summary
Integrated circuits such as application specific integrated circuits or programmable logic devices may include sequential elements such as configurable register circuitry. Such configurable register circuitry may operate as independent registers controlled by selectable clock signals or as a single register with error detection and error correction capabilities. For example, the configurable register circuitry when operated as single register with error detection and error correction circuitry may detect and correct runtime errors caused by manufacturing and environmental variations, thereby allowing an increase in the clock rate that controls the register. If desired, the configurable register circuitry may be configured to detect single event upsets, which may enable the implementation of safe finite state machines.