Configurable Resettable Memory with Dynamic Logic Sampling
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Solution Overview
Problem
Conventional approaches to implementing a reset function in non-resettable memory units lack flexibility, as the reset value is fixed and cannot be changed without redesigning or recompiling the circuit, making it inconvenient and time-consuming.
Innovation Solution
A resettable memory device is designed with a memory unit, a reset status indicator circuit, and a sequential logic sampling circuit, allowing configurable reset values to be set based on user input or detected events, using a multiplexer to output either stored values or reset values depending on the reset status, and generating reset signals synchronously with clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a non-resettable memory unit is used with a fixed reset value, then the circuit structure is simple, but the adaptability to change reset values is poor
Solution Approach 1:
The patent implements dynamic reset values by using a sequential logic sampling circuit that can load different reset values at different times based on clock cycles and control signals. This allows the reset function to adapt to changing requirements without fixing the reset value to a constant, thereby improving adaptability while maintaining reasonable circuit complexity through dynamic reconfiguration.
Solution Approach 2:
The patent changes the parameter of reset value from a fixed constant to a variable that can be configured through control logic. By using control signals and sequential logic circuits, the reset value parameter becomes adjustable and reconfigurable, allowing the same memory unit to serve different purposes with different reset values without hardware changes.
2Adaptability or versatility
If the reset value is changed by redesigning or recompiling the circuit, then the reset value can be changed, but the time consumption increases
Solution Approach 1:
The patent implements preliminary action by pre-configuring multiple possible reset values in the sequential logic sampling circuit before they are needed. When a reset operation is required, the appropriate pre-configured value can be immediately loaded and applied without requiring redesign or recompilation. This allows rapid switching between different reset scenarios, eliminating time-consuming redesign cycles.
3Adaptability or versatility
If a multiplexer and sequential logic circuit are added to enable configurable reset values, then the adaptability improves, but the device complexity increases
Solution Approach 1:
The patent applies universality by designing the sequential logic sampling circuit to perform multiple functions: it can load reset values, hold reset values, select between different reset values based on control signals, and interface with the memory unit. This multi-functional approach consolidates what could be multiple separate components into a unified circuit structure, improving adaptability while limiting the increase in overall device complexity.
Data Source
AI summary
Disclosed is a resettable memory device including a memory unit, a reset status indicator circuit, a logic sampling circuit, and a multiplexer for performing a reset function. The memory unit includes cells for storing states of signals in a design under test. The reset status indicator stores states of indicators indicating whether corresponding cells should be reset or not. Responsive to the reset status indicator indicating that the value of the cell should not be reset, the multiplexer receives the value stored in the cell and outputs the retrieved value from the cell. Responsive to the reset status indicator indicating that the value of the cell should be reset, the multiplexer outputs a reset value instead of the value stored in the cell. The reset value may be changed by the logic sampling circuit at different time periods or certain logic conditions, and output through the multiplexer.