Configurable Reset Terminal Circuit for Processing Systems
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Solution Overview
Problem
Modern processing systems face challenges in managing reset operations due to increasing complexity and diverse application requirements, which traditional hardwired reset configurations cannot adequately address.
Innovation Solution
The implementation of configurable reset terminals and a reset management circuit that uses configuration data to dynamically control the behavior of reset pins, allowing for various reset configurations and scenarios to be accommodated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional hardwired reset configurations are used, then device complexity is reduced, but adaptability and versatility are limited
Solution Approach 1:
The reset management circuit dynamically configures reset terminals based on operational mode signals, transitioning between fixed hardwired connections and reconfigurable states. This allows the system to adapt reset behavior to different operational modes (e.g., normal operation, test mode, power-saving mode) without permanent hardware changes, resolving the contradiction between adaptability and complexity.
Solution Approach 2:
The invention changes the parameters of reset terminals by introducing configurability through mode signals and control logic. Reset terminals can be dynamically enabled or disabled, switched between input/output modes, or connected to different internal circuits based on operational requirements. This parameter change approach provides adaptability while managing complexity through systematic control mechanisms.
2Adaptability or versatility
If configurable reset terminals are implemented, then adaptability and versatility improve, but device complexity increases
Solution Approach 1:
The reset management circuit is designed as a universal multi-functional block that handles multiple reset-related functions: generating reset signals, configuring terminal behavior, managing internal/external reset sources, and supporting different operational modes. By consolidating these diverse functions into a single universal circuit, the invention achieves high adaptability without proportionally increasing overall system complexity.
Solution Approach 2:
The reset management circuit acts as an intermediary between the complex configurable reset terminals and the simpler processing system components. It absorbs the complexity of configuration management, providing a simplified interface to the rest of the system while enabling diverse reset terminal behaviors through internal control mechanisms and mode signals.
3Adaptability or versatility
If multiple reset configurations are supported, then adaptability improves, but ease of operation decreases
Solution Approach 1:
The reset management circuit incorporates feedback mechanisms that monitor the current operational mode and automatically adjust reset terminal configurations accordingly. Mode detection circuits provide feedback about system state, enabling the reset management logic to automatically select appropriate configurations without requiring manual intervention, thus maintaining ease of operation while supporting multiple scenarios.
Solution Approach 2:
The reset management circuit performs self-configuration based on detected operational conditions and stored configuration data. It automatically enables or disables terminals, selects appropriate reset sources, and adjusts terminal behavior without external control, making the system easy to operate while providing adaptable reset configurations for different applications.
Data Source
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AI summary
A processing system (10a) is described. The processing system comprises a microprocessor, a reset circuit (116a), a non-volatile memory having stored configuration data, a plurality of configuration data clients (112) and a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data to the configuration data clients (112). In response to switching on the processing system (10a), the processing system (10a) executes a reset phase (DR), a configuration phase (CP1) and a software runtime phase (SW). In particular, the processing system (10a) comprises a first reset terminal (RPa) having associated a first circuitry (30a, 32a) and a second reset terminal (RPb) having associated a first circuitry (30a, 32a), wherein the first circuitry (30a, 32a) and the second circuitry (30b, 32b) have associated at least one configuration data client (112a, 112b), and wherein the configuration data comprise first mode configuration data (MCDa) for the first terminal (RPa) and second mode configuration data (MCDb) for the second terminal (RPb). During the reset phase (DR) and the configuration phase (CP1) the first circuitry (30a, 32a) activates a strong pull-down resistance, and the second circuitry (30b, 32b) activate a weak pull-down resistance. Conversely, once the configuration phase is completed, and in particular during the software runtime phase (SW), the first circuitry (30a, 32a) may activate a weak pull-down resistance, e.g., for implementing a bi-direction reset terminal, or a weak pull-up resistance, e.g., for implementing a reset output terminal. Conversely, the second circuitry (30b, 32b) may activate a weak or strong pull-up resistance, e.g., for implementing a reset output terminal, or maintain activated the weak pull-down resistance, e.g., for implementing a reset input terminal.