Configurable Scan Chain Segmentation for Lower Debug Latency
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Solution Overview
Problem
Existing integrated circuits face long latency and significant dynamic power overhead during debugging operations due to the transmission of read-back and write-back data through scan chains, which includes unused synchronous circuits, limiting the maximum frequency and efficiency of these operations.
Innovation Solution
A configurable scan chain that bypasses data registers and local sector managers, allowing direct access to core logic circuitry, and enables configuration of scan chain segments with specialized logic circuits to reduce latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transmitted through the full scan chain including unused synchronous circuits, then complete coverage of all circuits is achieved, but latency increases and maximum frequency is limited
Solution Approach 1:
The scan chain is segmented into multiple independent segments, each containing a subset of synchronous circuits. This allows the scan chain to be configured to include only the necessary segments for a given read-back or write-back operation, rather than traversing the entire chain. The segmentation enables selective activation of circuit segments, reducing the effective scan chain length and thereby decreasing latency while maintaining complete coverage capability when needed.
Solution Approach 2:
The scan chain is made dynamic and reconfigurable, allowing its structure to change based on the specific debugging operation requirements. The scan chain can be dynamically reconfigured to include different combinations of synchronous circuit segments depending on which circuits need to be accessed. This dynamic adaptability enables the system to optimize latency for each specific operation while maintaining the ability to cover all circuits when necessary.
2Reliability
If data is transmitted through unused synchronous circuits, then all circuits are included in the scan chain, but dynamic power consumption increases
Solution Approach 1:
By segmenting the scan chain into independent sections, the system can selectively activate only those segments corresponding to circuits that need to be accessed during debugging. Unused segments remain inactive, preventing unnecessary switching activity and reducing dynamic power consumption. This segmented approach maintains the capability to include all circuits when necessary while enabling significant power savings during operations limited to specific circuit regions.
Solution Approach 2:
Different segments of the scan chain are independently controlled, allowing local optimization of power consumption. Only the local segments required for the current read-back or write-back operation are activated, while other segments remain in a low-power state. This localized activation strategy reduces overall dynamic power consumption compared to activating the entire scan chain, while preserving the ability to access any circuit when needed.
3Device complexity
If conventional scan chains are used, then simple implementation is maintained, but throughput of read-back and write-back operations is limited
Solution Approach 1:
The scan chain is divided into multiple independently controllable segments, each capable of being activated or deactivated based on operational needs. This segmentation enables parallel processing of data across multiple segments, significantly increasing the throughput of read-back and write-back operations. The segmented structure can be implemented using standard scan chain infrastructure with additional control logic, maintaining relative simplicity while achieving high throughput.
Solution Approach 2:
The scan chain incorporates dynamic reconfiguration capabilities that allow it to adapt its structure based on the specific debugging operations being performed. This dynamic behavior enables optimized data paths that maximize throughput for each operation type. The dynamic control mechanism adds manageable complexity to the scan chain, enabling high throughput without requiring a complete redesign of the scanning infrastructure.
Data Source
AI summary
An integrated circuit includes first and second data storage circuits, first, second, and third shadow storage circuits, and first, second, and third multiplexer circuits. The first multiplexer circuit is configurable to provide a state of a data signal from the first data storage circuit to the first shadow storage circuit in a snapshot mode. The second multiplexer circuit is coupled between an output of the second data storage circuit and an input of the second shadow storage circuit. The third multiplexer circuit is coupled to the second multiplexer circuit. The third multiplexer circuit is configurable to provide a state of an output signal of the first shadow storage circuit to an input of the third shadow storage circuit in a scan mode bypassing the second shadow storage circuit.