Configurable Scheduler for Graph Processing on Multi-Processor Systems

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Solution Overview

Problem

Multi-processor systems face challenges in efficiently managing code execution and data dependency, leading to reduced throughput in computation-rich applications, as existing methods struggle to effectively schedule code blocks across multiple processors.

Innovation Solution

A system comprising a compiler and scheduler that partitions code into blocks, schedules their execution across a processor array, and manages data buffers to ensure independent execution, utilizing a network topology for efficient data access and processing, thereby addressing data dependency and improving throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If code is executed in parallel on multiple processors, then throughput is improved, but data dependency management becomes more complex

Engineering Contradiction:
ImprovethroughputVSAvoiddata dependency management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The code is divided into discrete code blocks that can be independently scheduled and executed on different processors. This segmentation allows the parallel execution framework to manage data dependencies at the block level rather than at the instruction level, reducing the complexity of dependency tracking while maintaining high throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A scheduler component is introduced as an intermediary between the code blocks and processors. The scheduler analyzes data dependencies, determines execution order, and assigns code blocks to appropriate processors, thereby managing the complexity of parallel execution without requiring the application code to be modified.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If code is broken into smaller code blocks for parallel execution, then throughput is improved, but scheduling complexity increases

Engineering Contradiction:
ImprovethroughputVSAvoidscheduling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Code blocks are pre-analyzed and annotated with dependency information during compilation or code generation. This preliminary action allows the scheduler to efficiently determine execution order without performing complex real-time analysis, reducing scheduling complexity while enabling effective parallel execution.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If data dependency is considered when scheduling processors, then execution correctness is improved, but processing efficiency decreases

Engineering Contradiction:
Improveexecution correctnessVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By segmenting code into blocks with well-defined data dependencies, the system can identify independent blocks that can execute in parallel. This segmentation allows correctness to be maintained through dependency tracking at block boundaries while maximizing parallel execution of independent blocks, thus maintaining processing efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The scheduler dynamically adjusts the execution plan based on data dependency analysis, identifying the maximum parallel execution opportunities. This dynamic scheduling ensures correctness by respecting dependency constraints while optimizing for parallel execution, preventing the efficiency degradation that would result from overly conservative sequential scheduling.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11755368B2Configurable scheduler for graph processing on multi-processor computing systems
Publication Date: 2023.09.12 BLAIZE INC
  • US11755368B2 patent drawing
  • US11755368B2 patent drawing
  • US11755368B2 patent drawing

AI summary

Systems and methods are disclosures for scheduling code in a multiprocessor system. Code is portioned into code blocks by a compiler. The compiler schedules execution of code blocks in nodes. The nodes are connected in a directed acyclical graph with a top node, terminal node and a plurality of intermediate nodes. Execution of the top node is initiated by the compiler. After executing at least one instance of the top node, an instruction in the code block indicates to the scheduler to initiate at least one intermediary node. The scheduler schedules a thread for execution of the intermediary node. The data for the nodes resides in a plurality of data buffers; the index to the data buffer is stored in a command buffer.