Configurable Built-In Self-Repair Chain for Memory Test
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Solution Overview
Problem
Current high-density semiconductors with embedded memories face challenges in efficient manufacture and in-system test and repair due to the serial nature of data delivery through conventional scan networks, which can be time-consuming for circuits with hundreds or thousands of memories.
Innovation Solution
A configurable built-in self-repair chain is introduced, utilizing a scan network that divides repair registers into segments and employs segment selection devices to optimize the scan path, allowing for parallel shifting of repair information and segment selection bits, thereby reducing the time required for loading and unloading repair data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional scan network is used to transport repair information serially, then the device complexity is reduced, but the productivity deteriorates due to excessive time required for loading and unloading repair data
Solution Approach 1:
The repair register is divided into multiple segments (first repair register segment, second repair register segment, etc.), each with its own segment selection device. This segmentation allows parallel processing of repair information across different segments, significantly reducing the time required to load and unload repair data compared to a conventional serial scan network.
Solution Approach 2:
The patent transitions from a one-dimensional serial data delivery approach to a multi-dimensional parallel architecture by introducing segment selection devices that can independently control data flow through different segments. This dimensional change enables simultaneous data operations across multiple segments, improving productivity without proportionally increasing complexity.
2Reliability
If the scan path includes all repair register segments, then complete repair information coverage is achieved, but the time required for data shifting increases
Solution Approach 1:
The segment selection devices dynamically configure the scan path based on which segments contain defective memories. The selection logic adaptively includes only the necessary segments in the active scan path, ensuring complete coverage of defective segments while excluding functional segments from the data shifting process, thereby reducing overall time without compromising repair information completeness.
Solution Approach 2:
Different segments of the repair register are treated differently based on their content - segments containing defective memories are included in the scan path with full processing, while segments without defects are excluded. This local quality approach ensures that repair information completeness is maintained for defective segments while minimizing time loss by excluding functional segments.
Data Source
AI summary
A scan network configured to transport repair information between memories and a controller for a non-volatile storage device comprises: repair registers coupled in parallel to repair information generation circuitry for one of the memories and segment selection devices that divide the repair registers into repair register segments. Each of the segment selection devices comprises: a storage element configured to store a segment selection bit and segment selection bit generation circuitry configured to generate the segment selection bit based on the repair information. Each of the segment selection devices is configurable to include or not include the corresponding repair register segment in a scan path of the scan network in a shift operation based on the segment selection bit.