Configurable State Transition for VLSI Verification
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Solution Overview
Problem
Current hardware design verification methods face challenges in efficiently verifying numerous functions across various states of semiconductor integrated circuits, as fully randomized test cases are unreliable and tightly constrained test cases are labor-intensive, making it difficult to achieve desired states in test models.
Innovation Solution
A computer-implemented method that generates and executes a test sequence to transition resources within an integrated circuit from an existing state to a target state, using a state object to specify the target state value and automated instruction generation to produce instructions for achieving these states, thereby enhancing random test case generation and coverage analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If fully randomized test cases are used, then little effort is required from design engineers, but the reliability of achieving desired states in test models is low
Solution Approach 1:
The test case generation system dynamically adjusts the level of randomization and constraint based on verification needs. The instruction sequence generator can operate in different modes (fully randomized, partially constrained, or tightly specified) and can adapt the degree of freedom in test case generation to balance engineer effort against state achievement reliability.
Solution Approach 2:
The system changes parameters of test case generation by introducing configurable constraints on instruction sequences. Instead of fixed fully randomized or fixed tightly specified approaches, the system allows parameter adjustment of randomization levels, constraint tightness, and state transition requirements to optimize both ease of operation and reliability.
2Reliability
If tightly constrained test cases are used, then the reliability of achieving desired states in test models is improved, but the device complexity and labor intensity increase
Solution Approach 1:
The instruction sequence generator performs self-service by automatically generating constrained test cases without requiring manual intervention. The system autonomously creates instruction sequences that satisfy specified state transitions, eliminating the labor-intensive manual test vector writing while maintaining tight constraints for reliable state achievement.
Solution Approach 2:
The system replaces the mechanical process of manual test case construction with an automated computational generator. Instead of engineers manually creating tightly constrained test cases (mechanical process), an algorithmic instruction sequence generator automatically produces the test vectors, reducing complexity while maintaining reliability.
3Reliability
If the number of functions to be verified increases, then the coverage of verification is improved, but the time required to verify all functions across different states increases
Solution Approach 1:
The system performs preliminary action by pre-generating instruction sequences that are designed to reach specific target states. Instead of executing random instructions and hoping to reach desired states, the generator pre-computes the instruction sequences needed to achieve verification coverage, reducing the time required to verify multiple functions across different states.
Solution Approach 2:
The instruction sequence generator maintains continuity of useful action by systematically generating test cases that continuously progress through different states and functions. The generator ensures continuous verification coverage by methodically creating instruction sequences that traverse the state space, preventing gaps in verification while minimizing total verification time.
Data Source
AI summary
According to one aspect of the present disclosure a system and method of enhancing random test case generation during pre-silicon design verification of test models of very large scale integration (VLSI) processors and systems is provided. A test sequence including a specification of at least one target state value for at least one resource of the hardware design model is received and includes a state object having at least one state element defining the target state value for a resource. Instructions are generated to transition the at least one resource from an existing state to the at least one target state value. The instructions are executed according to the test sequence to transition the resources to the defined state. State information on the hardware design model is output to allow a process engineer to determine whether the target state value for the resource was successfully changed.