Configurable Storage Circuit With Embedded Processing
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Solution Overview
Problem
Configurable storage blocks in integrated circuits often execute common memory operations inefficiently, particularly read-modify-write operations, which require multiple clock cycles and can lead to routing congestion due to the need to provide memory addresses for both read and write operations, even when they target the same address.
Innovation Solution
Incorporating a configurable control circuit and processing circuit within the storage block to decode instructions, perform data processing, and manage memory access operations, allowing for reduced latency and increased throughput by minimizing the need for input and output ports and optimizing memory bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If read-modify-write operations are implemented using traditional configurable storage blocks, then the operations can be performed, but they require multiple clock cycles and cause routing congestion
Solution Approach 1:
The patent combines the memory array with embedded processing circuitry and control logic into a unified storage block. This merging allows read-modify-write operations to be executed within the same circuit block without requiring separate read and write cycles through external routing, thereby reducing the number of clock cycles needed and eliminating routing congestion.
Solution Approach 2:
The patent introduces an intermediary control circuit within the storage block that manages read-modify-write operations internally. This control circuit coordinates between the memory array and processing elements, enabling efficient operation execution without external intervention and reducing the time required compared to traditional approaches.
2Ease of operation
If address lines are provided for both read and write operations, then memory access can be controlled, but routing congestion increases when addresses are known in advance
Solution Approach 1:
The patent implements preliminary action by having the control circuit identify and prepare write addresses in advance within the storage block. When the address for a write operation is known beforehand, the control logic can pre-position the address information internally, eliminating the need for external address lines and reducing routing complexity.
Solution Approach 2:
The patent creates a universal control circuit that handles both read and write operations through a unified internal addressing mechanism. This multi-functional control logic can manage different operation types without requiring separate external address routing paths, thereby reducing overall routing congestion while maintaining ease of operation.
3Adaptability or versatility
If multiple input and output ports are used for memory operations, then operation flexibility is maintained, but latency increases
Solution Approach 1:
The patent merges multiple input and output ports into a unified internal data path within the storage block. By combining these interfaces and routing data through integrated internal pathways rather than external connections, the system maintains operational flexibility while significantly reducing the latency associated with external signal traversal.
Data Source
AI summary
An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, a processing circuit, and a configurable control circuit. The configurable storage block may receive an instruction which may be decoded in the control block to identify a command. The command may be associated with a pre-defined sequence of operations that the control block executes by directing the memory array to perform memory access operations and the processing circuit to execute data processing operations. These data processing operations may be executed on data retrieved during memory access operations, data received subsequent to receiving the instruction, or previously computed data. The processed data may be provided for further processing outside the configurable storage block or stored in the memory array. The configurable storage block may further have delay blocks to allow for delayed memory access to the memory array.