Configurable Storage Blocks with Embedded FIFO and Delay Lines
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Solution Overview
Problem
Conventional configurable storage blocks in integrated circuits are often underutilized, as they are typically designed for pure memory use, leaving unused resources and requiring specific logic and routing for implementations like FIFO, shift registers, or delay-line modules, which can lead to routing congestion and performance issues.
Innovation Solution
A configurable storage block that includes an address port, memory array, arithmetic circuitry, and control circuitry, allowing for flexible access modes such as random-access, FIFO, shift register, or delay-line modes, enabling efficient implementation of these designs without the need for additional specific logic and routing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If configurable storage blocks are designed for pure memory use, then memory functionality is provided, but additional specific logic and routing resources are required for FIFO, shift register, or delay-line implementations
Solution Approach 1:
The storage block is enhanced with arithmetic circuitry and control circuitry that enable it to perform multiple functions including random-access memory, FIFO, shift register, and delay-line operations. The arithmetic circuitry generates addresses based on arithmetic operations (increment, decrement, multiply, divide) while the control circuitry selects between different access modes, allowing a single block to replace multiple specialized components.
Solution Approach 2:
The patent combines memory array, arithmetic circuitry, and control circuitry into a single integrated storage block. The arithmetic circuitry includes counters, incrementers, and multiplexers that are merged with the memory structure, eliminating the need for separate logic and routing resources that would otherwise be required for specialized implementations.
2Ease of operation
If conventional storage blocks are used for FIFO or shift register implementations, then routing congestion occurs, but pure memory design does not provide sequential access capabilities
Solution Approach 1:
The storage block provides both random-access memory functionality and sequential access capabilities (FIFO, shift register, delay-line) within the same integrated structure. The control circuitry selects between address port input (for random access) and arithmetic circuitry output (for sequential access), eliminating routing congestion while maintaining all access modes.
Solution Approach 2:
The arithmetic circuitry acts as an intermediary between the address port and memory array, generating addresses through arithmetic operations. This intermediary structure enables sequential access patterns without requiring external logic circuits, thereby reducing routing congestion while providing FIFO and shift register functionality.
3Reliability
If specialized logic and routing are added for FIFO implementations, then FIFO functionality is achieved, but resource usage increases and timing becomes less deterministic
Solution Approach 1:
The storage block is designed to provide FIFO functionality along with other access modes through integrated arithmetic and control circuitry. The arithmetic circuitry generates addresses using counters and incrementers that operate synchronously with the memory, providing deterministic timing without requiring external specialized logic resources.
Data Source
AI summary
An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, an arithmetic circuit, and a control circuit. The control circuit may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement first-in first-out modules, shift registers, or delay-line modules in addition to implementing memory modules with random access.