Configurable Storage Circuit for Finite-State Machine Implementation
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Solution Overview
Problem
Conventional configurable storage blocks in integrated circuits are underutilized, leading to inefficiencies in implementing complex user designs, as they typically support only a pure memory use model and provide a fixed number of blocks, resulting in unused capacity and increased resource usage for finite-state machine implementations.
Innovation Solution
Incorporating a modified configurable storage block with additional circuitry, including a processing circuit and state registers, which allows for the efficient implementation of finite-state machines by computing addresses and storing data, thereby reducing the need for specific logic and routing resources and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional configurable storage blocks are used with a fixed number of blocks, then the device structure is simple, but the utilization efficiency is low and capacity is wasted
Solution Approach 1:
The patent implements dynamic configurability where the number of storage blocks can be changed based on design requirements. The configurable storage block allows users to define the number of blocks, depth, and width according to their specific finite-state machine implementation needs, transforming a static fixed structure into a dynamic adaptable one that optimizes resource utilization.
Solution Approach 2:
The configurable storage block serves multiple functions: it acts as both storage memory and control logic for finite-state machines. The same block can be reconfigured for different applications and depths without requiring separate dedicated blocks, making the storage structure universal and multi-functional rather than purpose-specific.
2Adaptability or versatility
If conventional storage blocks support only pure memory use model, then the circuit is simple, but the adaptability for finite-state machine implementations is limited
Solution Approach 1:
The configurable storage block is designed to serve dual purposes: traditional memory storage operations and finite-state machine control logic. By integrating address computation, state storage, and transition control within the same block, the patent enables the storage structure to adapt to different implementation models including pure memory, FSM-based control, and hybrid approaches.
Solution Approach 2:
The patent merges the storage function with the control function by implementing address computation logic and state management capabilities directly within the configurable storage block. This combination allows the same hardware structure to handle both data storage and finite-state machine operations, eliminating the need for separate dedicated control logic blocks.
3Productivity
If more storage blocks are allocated to handle complex designs, then the capacity is sufficient, but the unused capacity increases and resource usage increases
Solution Approach 1:
The system dynamically configures the number of storage blocks based on the specific design requirements rather than allocating a fixed maximum number. Users can specify the exact number of blocks needed for their finite-state machine implementation, allowing the resource quantity to adapt to actual usage patterns and eliminate wasted capacity.
Solution Approach 2:
The patent allows changing key parameters including the number of storage blocks, depth, and width according to design needs. By making these parameters configurable rather than fixed, the system can optimize resource allocation to match the actual computational requirements of different finite-state machine implementations.
Data Source
AI summary
An integrated circuit may have circuitry that includes a storage circuit, a processing circuit, and at least one state register to implement a finite-state machine. The storage circuit may store base addresses and output data for each state of the finite-state machine. The storage circuit may further store offset values that are based on the input data to the finite-state machine and the state transition from a current state to a next state caused by the input data. The processing circuit may compute the address of the storage circuit location where the output data of the next state is stored. The computation of this address may depend on the offset value and base address of the current state. The state register may receive the address from the processing circuit, store the address, and perform the corresponding memory access operation on the storage circuit.