Configurable Storage Circuits for Low-Latency Signal State Readback
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Solution Overview
Problem
Current methods for verifying gate-level representations of circuit designs in configurable integrated circuits face long execution times and significant dynamic power overhead due to high latency and power consumption during non-destructive register readback and writeback operations, especially when using full scan chains that include unused synchronous circuits.
Innovation Solution
The integration of first and second configurable storage circuits in a scan chain within the integrated circuit, configured to perform non-destructive register readback and writeback operations, where the first storage circuit stores the state of a synchronous circuit and the second storage circuit stores the output of the first, allowing for efficient sampling and tracing of signal states during emulation mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full scan chains including all synchronous circuits are used for readback and writeback operations, then complete circuit state verification is achieved, but execution time and dynamic power consumption increase significantly
Solution Approach 1:
The patent segments the scan chain into two distinct parts: a first scan chain containing only used synchronous circuits, and a second scan chain containing unused synchronous circuits. This segmentation allows readback and writeback operations to selectively use only the first scan chain, excluding unused circuits from the operation path, thereby reducing execution time while maintaining verification completeness for functional circuits.
Solution Approach 2:
The patent extracts unused synchronous circuits from the readback and writeback path by placing them in a separate second scan chain. This extraction removes the harmful factor (unused circuits causing delay) while preserving the useful function (verification of used circuits) through the first scan chain.
2Reliability
If full scan chains including all synchronous circuits are used for readback and writeback operations, then complete circuit state verification is achieved, but dynamic power overhead increases due to toggling of unused circuits
Solution Approach 1:
The patent segments the scan chain into two distinct parts: a first scan chain containing only used synchronous circuits, and a second scan chain containing unused synchronous circuits. This segmentation allows readback and writeback operations to selectively use only the first scan chain, excluding unused circuits from the operation path, thereby reducing dynamic power consumption while maintaining verification completeness for functional circuits.
Solution Approach 2:
The patent extracts unused synchronous circuits from the readback and writeback path by placing them in a separate second scan chain. This extraction removes the harmful factor (unused circuits causing power consumption) while preserving the useful function (verification of used circuits) through the first scan chain.
3Device complexity
If traditional single storage circuit approach is used, then circuit structure is simpler, but latency during readback operations increases
Solution Approach 1:
The patent merges a first storage circuit and a second storage circuit into a unified dual-storage system. The first storage circuit holds current states of used synchronous circuits, while the second storage circuit holds previous states. This merging enables simultaneous readback of current and previous states, reducing latency by providing both states without sequential access delays.
Solution Approach 2:
The second storage circuit preliminarily stores previous states of synchronous circuits before they are needed for comparison or analysis. By having previous states pre-loaded and readily available, the system eliminates the need to sequentially retrieve or recalculate them, thereby reducing readback latency.
Data Source
AI summary
An integrated circuit includes a logic circuit block that includes a first adaptive logic module configurable to store a first state of a first signal received from a device-under-test in a first register, a second adaptive logic module configurable to store a second state of a second signal in a second register during a user mode of the integrated circuit simultaneously with the first state of the first signal being stored in the first register, and a third adaptive logic module configurable to store a third state of the first signal in a third register. The first and the third states of the first signal are stored for consecutive clock cycles in the first register and the third register. The logic circuit block is configurable to scan out the second state in the second register and the third state in the third register.