Configurable Data Stream Processor Without Memory Round Trips

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In traditional SoC architectures, system components require memory round trips to retrieve and share data, leading to inefficiencies and increased power consumption due to asynchronous memory operations.

Innovation Solution

A data stream processor with direct electronic communication between processing entities, utilizing a streamed data transceiver interface, configurable processing units, and a configuration unit to transform data formats and contents directly, bypassing memory fetches and stores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory-mapped interconnect architecture is used for data transfer between system components, then data sharing capability is improved, but processing efficiency deteriorates due to memory round trips

Engineering Contradiction:
Improvedata sharing capabilityVSAvoidprocessing efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent introduces a stream processor as an intermediary component between system components, enabling direct data streaming and processing without requiring memory round trips. The stream processor receives data streams from one component and passes processed data to another component, acting as a mediator that eliminates the inefficiency of memory-based data transfer while maintaining data sharing capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If memory-mapped interconnect architecture is used for data transfer, then system integration is improved, but power consumption increases due to asynchronous memory operations

Engineering Contradiction:
Improvesystem integrationVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The stream processor serves as an intermediary that enables synchronous data streaming between components, eliminating the need for asynchronous memory operations. By directly passing data through the stream processor, the system reduces power consumption associated with memory access while maintaining system integration and data sharing capabilities.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If memory round trips are used for data retrieval, then data access flexibility is improved, but latency increases

Engineering Contradiction:
Improvedata access flexibilityVSAvoidlatency
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent implements continuous data streaming through the stream processor, where data flows continuously from source to destination without interruption. This continuous action eliminates the start-stop nature of memory round trips, reducing latency while maintaining data access flexibility. The stream processor maintains data flow continuity by directly passing data between components in real-time.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20250315439A1Data Stream Processor
Publication Date: 2025.10.09 ARM LTD
  • US20250315439A1 patent drawing
  • US20250315439A1 patent drawing
  • US20250315439A1 patent drawing

AI summary

Provided is a data stream processor comprising a streamed data transceiver interface, a structure of processing units configurable to transform data received from a data source over the streamed data transceiver interface according to a specified output requirement, and a configuration unit operable in electronic communication with a data consumer to receive an output requirement and to configure the operation and linkage of a processing unit in the structure of processing units to transform input data to output data according to the specified output requirement; wherein the structure of processing units is further operable to provide the output data for output over the streamed data transceiver interface.