Configurable Tap Digital Filter With Fixed Latency Processing
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Solution Overview
Problem
Traditional FIR filters experience processing delays and increased complexity as the number of taps increases, limiting their ability to process input samples at high rates and causing jitter, which can be problematic in applications like traveling wave-based relay protection.
Innovation Solution
A configurable digital filter with fixed latency, utilizing a shift register and adder, accumulator, and scaler circuits to process samples in a fixed number of clock cycles regardless of tap length, allowing for efficient sampling and processing at higher rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of taps in a traditional FIR filter is increased to improve filtering capability, then the filtering performance is improved, but the processing delay increases and the device complexity increases
Solution Approach 1:
The filter processing is segmented into distinct stages: a first plurality of registers receives and stores input samples, while a second plurality of registers processes tap values. This segmentation allows the filter to process samples through different paths simultaneously, reducing the overall processing delay while maintaining the required filtering performance with multiple taps.
Solution Approach 2:
The patent introduces a temporal dimension by processing samples in a pipelined manner across multiple clock cycles. Instead of processing all taps sequentially for each sample (which increases delay), the filter processes multiple samples through different tap stages in parallel across time, achieving both high filtering performance and reduced latency.
2Reliability
If the number of taps in a traditional FIR filter is increased to improve filtering capability, then the filtering performance is improved, but the device complexity increases
Solution Approach 1:
The register structures are designed to serve multiple functions: they store input samples, hold tap values, and facilitate data flow through the filtering stages. This multi-functionality reduces the need for separate dedicated components for each function, thereby reducing overall device complexity while supporting high tap counts for improved filtering performance.
Solution Approach 2:
The filter architecture uses dynamically configurable register assignments where the same physical registers can be assigned to different functional roles based on the operating mode and tap requirements. This dynamic allocation optimizes resource utilization and reduces the number of fixed dedicated components needed, lowering device complexity.
3Device complexity
If traditional FIR filters process samples sequentially to maintain simplicity, then the device complexity is reduced, but the processing speed decreases
Solution Approach 1:
The filter maintains continuous processing by pipelining the computation across multiple clock cycles. While one set of registers is computing the output for one sample, another set is simultaneously preparing the next sample. This continuous action across time enables high processing speed without requiring all computations to complete in a single cycle, thus maintaining reasonable device complexity.
Data Source
AI summary
A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles.