Configurable TCE Data Structure for PHB Die Area Reduction
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Solution Overview
Problem
Current data processing systems face challenges in efficiently managing and isolating I/O resources across multiple logical partitions, leading to increased complexity and resource allocation issues, particularly in handling DMA and I/O error messages, due to the large size of conventional Translation and Validation Tables (TVTs) within Peripheral Component Interconnect (PCI) host bridges (PHBs).
Innovation Solution
A configurable Translation Control Entry (TCE) data structure is implemented, allowing for one or more levels of TCE tables, which reduces the size of data structures within PHBs by eliminating unnecessary fields and using a RID Translation Table (RTT) and a streamlined TVT with a depth field to support multiple levels of TCE tables, enabling efficient address translation and error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional Translation and Validation Tables (TVTs) are used in PCI host bridges, then address translation functionality is provided, but the die area of PHBs increases due to the large size of data structures
Solution Approach 1:
The patent extracts the translation control entry (TCE) data structure from the Peripheral Component Interconnect (PCI) host bridge (PHB) and places it in system memory. This removal of the large TCE data structure from the PHB significantly reduces the die area of the PHB while maintaining the address translation functionality through the use of translation control entries in system memory that are accessed via translation control table (TCT) indices.
Solution Approach 2:
The patent segments the address translation functionality into multiple components: translation control entries (TCEs) stored in system memory, translation control tables (TCTs) that index into TCEs, and translation validation tables (TVTs) that provide validation information. This segmentation allows the PHB to maintain a smaller, more manageable data structure while still providing comprehensive address translation and validation capabilities.
2Productivity
If monolithic TCE tables are used, then performance is improved due to single memory access, but management becomes more difficult due to contiguous storage requirements
Solution Approach 1:
The patent implements a dynamic TCE table management system where the number of TCE tables and their sizes can be configured based on runtime requirements. The system can dynamically allocate and deallocate TCE table space in system memory, and the translation control entries can be organized into multiple tables rather than requiring a single monolithic structure. This dynamic approach allows flexible management while maintaining performance through efficient indexing mechanisms.
3Ease of operation
If multi-level TCE tables are used, then management becomes easier with non-contiguous storage, but performance decreases due to multiple memory accesses
Solution Approach 1:
The patent implements preliminary action by pre-organizing translation control entries into structured tables with indices before runtime operations. The translation control table (TCT) structure pre-computes and stores indices that directly point to relevant TCEs in system memory, eliminating the need for multi-level traversal during runtime address translation. This preliminary organization allows the system to achieve both easy management through structured data organization and high performance through direct indexed access.
Data Source
AI summary
In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.