Configurable Translation Lookaside Buffer with Dynamic Bank Allocation

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Solution Overview

Problem

Conventional translation lookaside buffers (TLBs) in microprocessors face challenges in achieving low latency and power efficiency, especially in superscalar processors with multiple pipelines, due to large multiported structures and support for multiple page sizes, which result in high area consumption and access times.

Innovation Solution

A dynamically configurable TLB with two independently configurable storages that allocate entries based on page sizes, allowing address translations to be copied between storages to optimize storage usage and reduce power consumption by dynamically reallocating sections based on page access patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional TLB structures include several large multiported structures to provide low latency to multiple pipelines, then access time is reduced, but area consumption and power consumption increase significantly

Engineering Contradiction:
Improveaccess timeVSAvoidpower consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The TLB is divided into multiple banks (first bank, second bank, third bank) that can be independently accessed. Each bank stores a subset of the total TLB entries, allowing parallel access operations. This segmentation enables multiple pipelines to access different banks simultaneously, reducing access latency without requiring a single large multiported structure that would consume excessive power and area.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a bank selection dimension to the TLB architecture. Instead of using a single large structure with multiple ports, the system uses multiple smaller banks selected through bank identification logic. The virtual address is used to determine which bank to access, adding a bank selection dimension that enables parallel access patterns while keeping individual bank structures small and power-efficient.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If very large fully associative TLB structures are used to support multiple page sizes, then versatility is improved, but area consumption and access times increase

Engineering Contradiction:
Improvesupport for multiple page sizesVSAvoidarea consumption
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The TLB entries are segmented across multiple banks, with each bank capable of storing translations for different page sizes. The first bank stores 4KB page translations, the second bank stores 2MB page translations, and the third bank stores 1GB page translations. This segmentation allows the system to support multiple page sizes without requiring a single large fully associative structure, thereby reducing area consumption while maintaining versatility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each bank is optimized for specific page sizes with dedicated entry structures. The first bank is configured for 4KB pages with specific field widths, the second bank for 2MB pages with different field configurations, and the third bank for 1GB pages. This local optimization allows each bank to be compact and efficient for its specific purpose, rather than designing a single large structure to handle all page sizes uniformly.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If multiple page sizes are supported in conventional TLB designs, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improvesupport for multiple page sizesVSAvoidstructure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The TLB is segmented into multiple banks, with each bank dedicated to specific page sizes. This segmentation simplifies the control logic within each bank, as each bank only needs to handle translations for its designated page sizes rather than managing all page sizes. The bank selection logic uses simple identification based on the virtual address to route requests to the appropriate bank, reducing overall device complexity compared to a single complex fully associative structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The TLB configuration is made dynamic through the bank selection mechanism. The system can dynamically select which bank to access based on the page size required by the current translation request. This dynamic bank selection allows the TLB to adapt to different page size requirements without requiring complex reconfiguration logic, as the appropriate bank is selected based on simple address-based identification.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7389402B2Microprocessor including a configurable translation lookaside buffer
Publication Date: 2008.06.17 MEDIATEK INC
  • US7389402B2 patent drawing
  • US7389402B2 patent drawing
  • US7389402B2 patent drawing

AI summary

A translation lookaside buffer may include control functionality coupled to a first storage and a second storage. The first storage includes a first plurality of entries for storing address translations corresponding to a plurality of page sizes. The second storage includes a second plurality of entries for storing address translations corresponding to the plurality of page sizes. In response to receiving a first address translation associated with a first page size, the control functionality may allocate the first plurality of entries to store address translations corresponding to the first page size. In addition, in response to receiving a request including an address that matches an address translation stored within the first storage, the control functionality may copy a matching address translation from the first storage to the second storage.