Configuration Bitstreams for PLD Timing Variation Reduction
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Solution Overview
Problem
Programmable logic devices (PLDs) face challenges due to their complex and large die size, leading to increased defects and high production costs, as well as the need for extensive qualification processes to ensure timing requirements are met, which can be time-consuming and expensive, especially when multiple bitstreams are involved.
Innovation Solution
A method is developed to analyze and modify implementations of a design to reduce timing variations among different bitstreams, ensuring that each implementation meets maximum and minimum timing constraints, thereby simplifying the validation process and enabling the use of defective PLDs by generating multiple configuration bitstreams that minimize variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple configuration bitstreams are generated for different implementations, then the ability to avoid defective logic is improved, but the timing variation among implementations increases
Solution Approach 1:
The patent modifies design parameters by adding delay elements to unconstrained nets and paths in each implementation. This parameter adjustment equalizes the timing characteristics across multiple implementations, ensuring that timing-critical paths meet maximum timing constraints while non-critical paths are deliberately slowed down. The result is reduced timing variation among implementations while maintaining the ability to avoid defective logic through multiple bitstream options
2Adaptability or versatility
If conventional design tools are used without timing constraints on all nets, then design flexibility is maintained, but timing variations among implementations increase
Solution Approach 1:
The patent applies different quality standards to different parts of the design by identifying and separately treating constrained and unconstrained nets. Constrained nets (timing-critical paths) are optimized to meet timing requirements, while unconstrained nets (non-critical paths) are deliberately modified to add delay. This local differentiation maintains design flexibility for critical paths while controlling timing variation through targeted modifications to non-critical paths
3Reliability
If extensive qualification processes are performed for multiple bitstreams, then timing requirement compliance is ensured, but validation time and cost increase
Solution Approach 1:
The patent performs preliminary timing analysis and modification during the design implementation phase, before validation. By proactively identifying timing-critical paths and adding appropriate delay elements to non-critical paths, the design is pre-conditioned to meet timing constraints. This preliminary action eliminates the need for extensive post-validation testing of multiple bitstreams, as the timing compliance is built into the implementations themselves
Data Source
AI summary
Methods of using one of a plurality of configuration bitstreams in an integrated circuit are disclosed. An exemplary method comprises analyzing the plurality of implementations of a design to determine initial variations in timing among the implementations; modifying the implementations to reduce the variations in timing among the implementations; and outputting a plurality of configuration bitstreams for the implementations having variations in timing that are reduced relative to the initial variations in timing. Another method comprises generating a plurality of implementations for the design; generating a cost function for the design based upon costs (e.g., collision penalties) derived from at least two of the plurality of implementations; determining a cost for each implementation based upon the cost function; optimizing an implementation of the design by minimizing the cost of the implementation; generating a plurality of configuration bitstreams for the plurality of implementations; and outputting the plurality of configuration bitstreams.