Configuration Memory Mapping for Loop-Parallel Reconfigurable Processors

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Solution Overview

Problem

Reconfigurable processors face inefficiencies in processing tasks with changed work contents due to fixed hardware functions, and software processing is slower, necessitating an optimization of configuration memory to enhance processing speed and utility, particularly in digital signal processing applications.

Innovation Solution

A method and apparatus for optimizing configuration memory in reconfigurable processors by analyzing parallelism in program code loops, scheduling function units, generating configuration data, and determining memory mapping strategies that include regular or irregular encoding and buffering, to efficiently store configuration data in configuration memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If configuration memory size is increased to store all loop cycle data, then processing completeness is improved, but memory resource consumption increases

Engineering Contradiction:

Improveprocessing completenessVSAvoidmemory resource consumption

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The configuration memory is segmented into multiple rows, with each row storing configuration data for a specific cycle or group of cycles. This allows selective storage of only necessary cycle data rather than storing all cycle data in a single large memory block, thereby reducing overall memory requirements while maintaining processing completeness.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system performs preliminary analysis of loop parallelism and schedules function unit groups before execution. This allows the memory mapping unit to determine in advance which cycles require configuration data storage and in which memory rows, optimizing memory usage before the actual processing begins.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If all function units are activated in each cycle to ensure processing capability, then processing versatility is improved, but configuration memory requirements increase

Engineering Contradiction:

Improveprocessing capabilityVSAvoidconfiguration memory requirements

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The system dynamically determines the number and configuration of function units activated in each cycle based on the analyzed parallelism of the loop. Instead of statically allocating all function units for every cycle, the activation is adjusted dynamically to match the actual processing requirements of each cycle, reducing configuration memory requirements while maintaining necessary processing versatility.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the activation parameters of function units based on cycle-specific requirements. By analyzing loop parallelism, the system determines optimal activation patterns for different cycles, changing which function units are active and in what configurations, thereby reducing the overall configuration memory footprint while preserving processing capability where needed.

Inventive Principle:

Principle #35Parameter changes

3Measurement precision

If configuration data is stored for every cycle to ensure accuracy, then processing accuracy is improved, but memory bandwidth consumption increases

Engineering Contradiction:

Improveprocessing accuracyVSAvoidmemory bandwidth consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The system extracts and stores only the essential configuration data needed for each cycle in dedicated memory rows, rather than storing redundant or unnecessary data. This selective extraction approach maintains processing accuracy by ensuring necessary data is available while reducing memory bandwidth consumption by eliminating unnecessary data transfers.

Inventive Principle:

Principle #2Taking out (Extraction)

4Ease of manufacture

If regular encoding is used for configuration data, then encoding simplicity is improved, but flexibility to handle varying function unit groups decreases

Engineering Contradiction:

Improveencoding simplicityVSAvoidflexibility

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The memory mapping unit employs a universal encoding approach that can handle both regular and irregular function unit group configurations. By designing the encoding scheme to be multi-functional, the system maintains encoding simplicity while adapting to varying function unit groups across different cycles, achieving both ease of implementation and operational flexibility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9727460B2Selecting a memory mapping scheme by determining a number of functional units activated in each cycle of a loop based on analyzing parallelism of a loop

Publication Date: 2017.08.08 SAMSUNG ELECTRONICS CO LTD

AI summary

A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.