Configuration RAM Error Location Circuitry for Soft Error Detection
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Solution Overview
Problem
Conventional programmable logic devices lack the ability to detect and locate soft errors in configuration random-access-memory cells, which can disrupt system operations, especially in critical applications, due to their inability to determine the location of errors within the memory array.
Innovation Solution
The integration of error detection and error location determination circuitry, including linear feedback shift register circuitry, pattern detection circuitry, and counter circuitry, which continuously monitors the configuration random-access-memory cells to identify the bit position of soft errors, allowing for appropriate error handling actions such as reloading configuration data or avoiding disruptive reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error detection circuitry is used to monitor configuration RAM cells, then error detection capability is provided, but the location of soft errors cannot be determined
Solution Approach 1:
The configuration RAM array is divided into multiple segments or regions, and the error detection circuitry is enhanced to identify which specific segment contains an error. This segmentation approach allows the system to locate errors at a granular level without requiring complete array reconfiguration, thus resolving the contradiction between detecting errors and obtaining location information.
2Reliability
If the entire configuration RAM array is monitored for errors, then comprehensive error detection is achieved, but system operation is disrupted when errors are detected
Solution Approach 1:
The error detection and handling approach treats different regions of the configuration RAM array differently. When an error is detected in a non-critical region, the system can continue operation by ignoring or bypassing only that specific local area rather than halting entire system operation. This local quality principle allows comprehensive monitoring while maintaining operational continuity for critical functions.
3Reliability
If configuration RAM cell design is modified to prevent soft errors, then error resistance is improved, but circuit complexity and real estate consumption increase
Solution Approach 1:
Instead of modifying the fundamental CRAM cell design to prevent errors, the invention implements feedback-based error detection and location circuitry that monitors the existing cells. This feedback approach provides error resistance through detection and management rather than through complex preventive design modifications, thus avoiding increased circuit complexity and real estate consumption while maintaining reliability.
Data Source
AI summary
Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of each array. The error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry contains linear feedback shift register circuitry that processes columns of array data. The circuitry continuously processes the data to identify the row and column location of each error.